atab-x86.c

It s a Linux disassemble, can set break point, disassemble ELF file.

  { I_FIMUL, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 1, { R_ST0, -1, -1 } },
  { I_FIMUL, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FINCSTP[] = {
  { I_FINCSTP, 0, { 0, 0, 0 }, "\xD9\xF7", 2, -1, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FINIT[] = {
  { I_FINIT, 0, { 0, 0, 0 }, "\x9B\xDB\xE3", 3, -1, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FIST[] = {
  { I_FIST, 2, { MEMORY|BITS16, REGISTER, 0 }, "\xDF", 1, 2, { -1, R_ST0, -1 } },
  { I_FIST, 2, { MEMORY|BITS32, REGISTER, 0 }, "\xDB", 1, 2, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FISTP[] = {
  { I_FISTP, 2, { MEMORY|BITS16, REGISTER, 0 }, "\xDF", 1, 3, { -1, R_ST0, -1 } },
  { I_FISTP, 2, { MEMORY|BITS32, REGISTER, 0 }, "\xDB", 1, 3, { -1, R_ST0, -1 } },
  { I_FISTP, 2, { MEMORY|BITS64, REGISTER, 0 }, "\xDF", 1, 7, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FISUB[] = {
  { I_FISUB, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 4, { R_ST0, -1, -1 } },
  { I_FISUB, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 4, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FISUBR[] = {
  { I_FISUBR, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xDA", 1, 5, { R_ST0, -1, -1 } },
  { I_FISUBR, 2, { REGISTER, MEMORY|BITS16, 0 }, "\xDE", 1, 5, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLD[] = {
  { I_FLD, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD9", 1, 0, { R_ST0, -1, -1 } },
  { I_FLD, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDD", 1, 0, { R_ST0, -1, -1 } },
  { I_FLD, 2, { REGISTER, MEMORY|BITS80, 0 }, "\xDB", 1, 5, { R_ST0, -1, -1 } },
  { I_FLD, 1, { REG_FPU, 0, 0 }, "\xD9\xC0", 2, FPUCODE, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLD1[] = {
  { I_FLD1, 1, { REGISTER, 0, 0 }, "\xD9\xE8", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLDCW[] = {
  { I_FLDCW, 1, { REGMEM, 0, 0 }, "\xD9", 1, 5, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLDENV[] = {
  { I_FLDENV, 1, { REGMEM, 0, 0 }, "\xD9", 1, 4, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLDL2E[] = {
  { I_FLDL2E, 1, { REGISTER, 0, 0 }, "\xD9\xEA", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLDL2T[] = {
  { I_FLDL2T, 1, { REGISTER, 0, 0 }, "\xD9\xE9", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLDLG2[] = {
  { I_FLDLG2, 1, { REGISTER, 0, 0 }, "\xD9\xEC", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLDLN2[] = {
  { I_FLDLN2, 1, { REGISTER, 0, 0 }, "\xD9\xED", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLDPI[] = {
  { I_FLDPI, 1, { REGISTER, 0, 0 }, "\xD9\xEB", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FLDZ[] = {
  { I_FLDZ, 1, { REGISTER, 0, 0 }, "\xD9\xEE", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FMUL[] = {
  { I_FMUL, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 1, { R_ST0, -1, -1 } },
  { I_FMUL, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 1, { R_ST0, -1, -1 } },
  { I_FMUL, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xC8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FMUL, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xC8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FMULP[] = {
  { I_FMULP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xC8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FNCLEX[] = {
  { I_FNCLEX, 0, { 0, 0, 0 }, "\xDB\xE2", 2, -1, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FNINIT[] = {
  { I_FNINIT, 0, { 0, 0, 0 }, "\xDB\xE3", 2, -1, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FNOP[] = {
  { I_FNOP, 0, { 0, 0, 0 }, "\xD9\xD0", 2, -1, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FNSAVE[] = {
  { I_FNSAVE, 2, { REGISTER, MEMORY, 0 }, "\xDD", 1, 6, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FNSTCW[] = {
  { I_FNSTCW, 1, { MEMORY, 0, 0 }, "\xD9", 1, 7, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FNSTENV[] = {
  { I_FNSTENV, 1, { MEMORY, 0, 0 }, "\xD9", 1, 6, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FNSTSW[] = {
  { I_FNSTSW, 1, { MEMORY|BITS16, 0, 0 }, "\xDD", 1, 7, { -1, -1, -1 } },
  { I_FNSTSW, 1, { REGISTER|BITS16, 0, 0 }, "\xDF\xE0", 2, -1, { R_AX, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FPATAN[] = {
  { I_FPATAN, 1, { REGISTER, 0, 0 }, "\xD9\xF3", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FPREM[] = {
  { I_FPREM, 1, { REGISTER, 0, 0 }, "\xD9\xF8", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FPREM1[] = {
  { I_FPREM1, 1, { REGISTER, 0, 0 }, "\xD9\xF5", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FPTAN[] = {
  { I_FPTAN, 1, { REGISTER, 0, 0 }, "\xD9\xF2", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FRNDINT[] = {
  { I_FRNDINT, 1, { REGISTER, 0, 0 }, "\xD9\xFC", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FRSTOR[] = {
  { I_FRSTOR, 2, { REGISTER, MEMORY, 0 }, "\xDD", 1, 4, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSAVE[] = {
  { I_FSAVE, 2, { REGISTER, MEMORY, 0 }, "\x9B\xDD", 2, 6, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSCALE[] = {
  { I_FSCALE, 1, { REGISTER, 0, 0 }, "\xD9\xFD", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSIN[] = {
  { I_FSIN, 1, { REGISTER, 0, 0 }, "\xD9\xFE", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSINCOS[] = {
  { I_FSINCOS, 1, { REGISTER, 0, 0 }, "\xD9\xFB", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSQRT[] = {
  { I_FSQRT, 1, { REGISTER, 0, 0 }, "\xD9\xFA", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FST[] = {
  { I_FST, 2, { MEMORY|BITS32, REGISTER, 0 }, "\xD9", 1, 2, { -1, R_ST0, -1 } },
  { I_FST, 2, { MEMORY|BITS64, REGISTER, 0 }, "\xDD", 1, 2, { -1, R_ST0, -1 } },
  { I_FST, 2, { REG_FPU, REGISTER, 0 }, "\xDD\xD0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSTCW[] = {
  { I_FSTCW, 1, { MEMORY, 0, 0 }, "\x9B\xD9", 2, 7, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSTENV[] = {
  { I_FSTENV, 1, { MEMORY, 0, 0 }, "\x9B\xD9", 2, 6, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSTP[] = {
  { I_FSTP, 2, { MEMORY|BITS32, REGISTER, 0 }, "\xD9", 1, 3, { -1, R_ST0, -1 } },
  { I_FSTP, 2, { MEMORY|BITS64, REGISTER, 0 }, "\xDD", 1, 3, { -1, R_ST0, -1 } },
  { I_FSTP, 2, { MEMORY|BITS80, REGISTER, 0 }, "\xDB", 1, 7, { -1, R_ST0, -1 } },
  { I_FSTP, 2, { REG_FPU, REGISTER, 0 }, "\xDD\xD8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSTSW[] = {
  { I_FSTSW, 1, { MEMORY, 0, 0 }, "\x9B\xDD", 2, 7, { -1, -1, -1 } },
  { I_FSTSW, 1, { REGISTER|BITS16, 0, 0 }, "\x9B\xDF\xE0", 3, -1, { R_AX, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSUB[] = {
  { I_FSUB, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 4, { R_ST0, -1, -1 } },
  { I_FSUB, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 4, { R_ST0, -1, -1 } },
  { I_FSUB, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xE0", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FSUB, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xE8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSUBP[] = {
  { I_FSUBP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xE8", 2, FPUCODE, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSUBR[] = {
  { I_FSUBR, 2, { REGISTER, MEMORY|BITS32, 0 }, "\xD8", 1, 5, { R_ST0, -1, -1 } },
  { I_FSUBR, 2, { REGISTER, MEMORY|BITS64, 0 }, "\xDC", 1, 5, { R_ST0, -1, -1 } },
  { I_FSUBR, 2, { REGISTER, REG_FPU, 0 }, "\xD8\xE8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { I_FSUBR, 2, { REG_FPU, REGISTER, 0 }, "\xDC\xE0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FSUBRP[] = {
  { I_FSUBRP, 2, { REG_FPU, REGISTER, 0 }, "\xDE\xE0", 2, FPUCODE, { -1, R_ST0, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FTST[] = {
  { I_FTST, 1, { REGISTER, 0, 0 }, "\xD9\xE4", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FUCOM[] = {
  { I_FUCOM, 1, { REG_FPU, 0, 0 }, "\xDD\xE0", 2, FPUCODE, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FUCOMI[] = {
  { I_FUCOMI, 2, { REGISTER, REG_FPU, 0 }, "\xDB\xE8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FUCOMIP[] = {
  { I_FUCOMIP, 2, { REGISTER, REG_FPU, 0 }, "\xDF\xE8", 2, FPUCODE, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FUCOMP[] = {
  { I_FUCOMP, 1, { REG_FPU, 0, 0 }, "\xDD\xE8", 2, FPUCODE, { -1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FUCOMPP[] = {
  { I_FUCOMPP, 1, { REGISTER, 0, 0 }, "\xDA\xE9", 2, -1, { R_ST1, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FXAM[] = {
  { I_FXAM, 1, { REGISTER, 0, 0 }, "\xD9\xE5", 2, -1, { R_ST0, -1, -1 } },
  { -1, -1, { -1, -1, -1 }, 0, -1, -1, { -1, -1, -1 } }
};

static struct x86OpCode Instruction_FXCH[] = {