dtab-x86.c

It s a Linux disassemble, can set break point, disassemble ELF file.

  { I_SMSW, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x01", 2, 4, { -1, -1, -1 } },
  { I_SMSW, 1, { MEMORY|BITS32, 0, 0 }, "\x0F\x01", 2, 4, { -1, -1, -1 } },
  { I_SQRTPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x51", 2, REGRM, { -1, -1, -1 } },
  { I_SQRTSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x51", 3, REGRM, { -1, -1, -1 } },
  { I_STC, 0, { 0, 0, 0 }, "\xF9", 1, -1, { -1, -1, -1 } },
  { I_STD, 0, { 0, 0, 0 }, "\xFD", 1, -1, { -1, -1, -1 } },
  { I_STI, 0, { 0, 0, 0 }, "\xFB", 1, -1, { -1, -1, -1 } },
  { I_STMXCSR, 1, { MEMORY|BITS32, 0, 0 }, "\x0F\xAE", 2, 3, { -1, -1, -1 } },
  { I_STOSB, 0, { 0, 0, 0 }, "\xAA", 1, -1, { -1, -1, -1 } },
  { I_STOSD, 0, { BITS32, 0, 0 }, "\xAB", 1, -1, { -1, -1, -1 } },
  { I_STOSW, 0, { 0, 0, 0 }, "\xAB", 1, -1, { -1, -1, -1 } },
  { I_STR, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 1, { -1, -1, -1 } },
  { I_SUB, 2, { REGISTER, IMMEDIATE|BITS8, 0 }, "\x2C", 1, -1, { R_AL, -1, -1 } },
  { I_SUB, 2, { REGISTER, IMMEDIATE|BITS16, 0 }, "\x2D", 1, -1, { R_AX, -1, -1 } },
  { I_SUB, 2, { REGISTER, IMMEDIATE|BITS32, 0 }, "\x2D", 1, -1, { R_EAX, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 5, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS8, REG8, 0 }, "\x28", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS16, REG16, 0 }, "\x29", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REGMEM|BITS32, REG32, 0 }, "\x29", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REG8, REGMEM|BITS8, 0 }, "\x2A", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REG16, REGMEM|BITS16, 0 }, "\x2B", 1, REGRM, { -1, -1, -1 } },
  { I_SUB, 2, { REG32, REGMEM|BITS32, 0 }, "\x2B", 1, REGRM, { -1, -1, -1 } },
  { I_SUBPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x5C", 2, REGRM, { -1, -1, -1 } },
  { I_SUBSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x5C", 3, REGRM, { -1, -1, -1 } },
  { I_SYSENTER, 0, { 0, 0, 0 }, "\x0F\x34", 2, -1, { -1, -1, -1 } },
  { I_SYSEXIT, 0, { 0, 0, 0 }, "\x0F\x35", 2, -1, { -1, -1, -1 } },
  { I_TEST, 2, { REGISTER, IMMEDIATE|BITS8, 0 }, "\xA8", 1, -1, { R_AL, -1, -1 } },
  { I_TEST, 2, { REGISTER, IMMEDIATE|BITS16, 0 }, "\xA9", 1, -1, { R_AX, -1, -1 } },
  { I_TEST, 2, { REGISTER, IMMEDIATE|BITS32, 0 }, "\xA9", 1, -1, { R_EAX, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xF6", 1, 0, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\xF7", 1, 0, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\xF7", 1, 0, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS8, REG8, 0 }, "\x84", 1, REGRM, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS16, REG16, 0 }, "\x85", 1, REGRM, { -1, -1, -1 } },
  { I_TEST, 2, { REGMEM|BITS32, REG32, 0 }, "\x85", 1, REGRM, { -1, -1, -1 } },
  { I_UCOMISS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x2E", 2, REGRM, { -1, -1, -1 } },
  { I_UD2, 0, { 0, 0, 0 }, "\x0F\x0B", 2, -1, { -1, -1, -1 } },
  { I_UNPCKHPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x15", 2, REGRM, { -1, -1, -1 } },
  { I_UNPCKLPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x14", 2, REGRM, { -1, -1, -1 } },
  { I_VERR, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 4, { -1, -1, -1 } },
  { I_VERW, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 5, { -1, -1, -1 } },
  { I_WAIT, 0, { 0, 0, 0 }, "\x9B", 1, -1, { -1, -1, -1 } },
  { I_WBINVD, 0, { 0, 0, 0 }, "\x0F\x09", 2, -1, { -1, -1, -1 } },
  { I_WRMSR, 0, { 0, 0, 0 }, "\x0F\x30", 2, -1, { -1, -1, -1 } },
  { I_XADD, 2, { REGMEM|BITS8, REG8, 0 }, "\x0F\xC0", 2, REGRM, { -1, -1, -1 } },
  { I_XADD, 2, { REGMEM|BITS16, REG16, 0 }, "\x0F\xC1", 2, REGRM, { -1, -1, -1 } },
  { I_XADD, 2, { REGMEM|BITS32, REG32, 0 }, "\x0F\xC1", 2, REGRM, { -1, -1, -1 } },
  { I_XCHG, 2, { REGISTER, REG16, 0 }, "\x90", 1, REGCODE, { R_AX, -1, -1 } },
  { I_XCHG, 2, { REGISTER, REG32, 0 }, "\x90", 1, REGCODE, { R_EAX, -1, -1 } },
  { I_XCHG, 2, { REG8, REGMEM|BITS8, 0 }, "\x86", 1, REGRM, { -1, -1, -1 } },
  { I_XCHG, 2, { REG16, REGMEM|BITS16, 0 }, "\x87", 1, REGRM, { -1, -1, -1 } },
  { I_XCHG, 2, { REG32, REGMEM|BITS32, 0 }, "\x87", 1, REGRM, { -1, -1, -1 } },
  { I_XLATB, 0, { 0, 0, 0 }, "\xD7", 1, -1, { -1, -1, -1 } },
  { I_XOR, 2, { REGISTER, IMMEDIATE|BITS8, 0 }, "\x34", 1, -1, { R_AL, -1, -1 } },
  { I_XOR, 2, { REGISTER, IMMEDIATE|BITS16, 0 }, "\x35", 1, -1, { R_AX, -1, -1 } },
  { I_XOR, 2, { REGISTER, IMMEDIATE|BITS32, 0 }, "\x35", 1, -1, { R_EAX, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 6, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS8, REG8, 0 }, "\x30", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS16, REG16, 0 }, "\x31", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REGMEM|BITS32, REG32, 0 }, "\x31", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REG8, REGMEM|BITS8, 0 }, "\x32", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REG16, REGMEM|BITS16, 0 }, "\x33", 1, REGRM, { -1, -1, -1 } },
  { I_XOR, 2, { REG32, REGMEM|BITS32, 0 }, "\x33", 1, REGRM, { -1, -1, -1 } },
  { I_XORPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x57", 2, REGRM, { -1, -1, -1 } },
  { 0, 0, { 0, 0, 0 }, 0, 0, 0, { 0, 0, 0 } }
};

static struct x86OpCode *OpCode_00[] = {
  Instructions + 28,
  0
};

static struct x86OpCode *OpCode_01[] = {
  Instructions + 29,
  Instructions + 30,
  0
};

static struct x86OpCode *OpCode_02[] = {
  Instructions + 31,
  0
};

static struct x86OpCode *OpCode_03[] = {
  Instructions + 32,
  Instructions + 33,
  0
};

static struct x86OpCode *OpCode_04[] = {
  Instructions + 20,
  0
};

static struct x86OpCode *OpCode_05[] = {
  Instructions + 21,
  Instructions + 22,
  0
};

static struct x86OpCode *OpCode_06[] = {
  Instructions + 591,
  0
};

static struct x86OpCode *OpCode_07[] = {
  Instructions + 537,
  0
};

static struct x86OpCode *OpCode_08[] = {
  Instructions + 485,
  0
};

static struct x86OpCode *OpCode_09[] = {
  Instructions + 486,
  Instructions + 487,
  0
};

static struct x86OpCode *OpCode_0A[] = {
  Instructions + 488,
  0
};

static struct x86OpCode *OpCode_0B[] = {
  Instructions + 489,
  Instructions + 490,
  0
};

static struct x86OpCode *OpCode_0C[] = {
  Instructions + 477,
  0
};

static struct x86OpCode *OpCode_0D[] = {
  Instructions + 478,
  Instructions + 479,
  0
};

static struct x86OpCode *OpCode_0E[] = {
  Instructions + 588,
  0
};

static struct x86OpCode *OpCode_0F[] = {
  Instructions + 34,
  Instructions + 52,
  Instructions + 53,
  Instructions + 54,
  Instructions + 55,
  Instructions + 56,
  Instructions + 57,
  Instructions + 58,
  Instructions + 59,
  Instructions + 60,
  Instructions + 61,
  Instructions + 62,
  Instructions + 63,
  Instructions + 64,
  Instructions + 65,
  Instructions + 66,
  Instructions + 67,
  Instructions + 68,
  Instructions + 69,
  Instructions + 70,
  Instructions + 71,