dtab-x86.c

It s a Linux disassemble, can set break point, disassemble ELF file.

  { I_POP, 1, { REGISTER, 0, 0 }, "\x0F\xA1", 2, -1, { R_FS, -1, -1 } },
  { I_POP, 1, { REGISTER, 0, 0 }, "\x0F\xA9", 2, -1, { R_GS, -1, -1 } },
  { I_POPA, 0, { 0, 0, 0 }, "\x61", 1, -1, { -1, -1, -1 } },
  { I_POPAD, 0, { BITS32, 0, 0 }, "\x61", 1, -1, { -1, -1, -1 } },
  { I_POPF, 0, { 0, 0, 0 }, "\x9D", 1, -1, { -1, -1, -1 } },
  { I_POPFD, 0, { BITS32, 0, 0 }, "\x9D", 1, -1, { -1, -1, -1 } },
  { I_POR, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xEB", 2, REGRM, { -1, -1, -1 } },
  { I_PREFETCHNTA, 1, { MEMORY|BITS8, 0, 0 }, "\x0F\x18", 2, 0, { -1, -1, -1 } },
  { I_PREFETCHT0, 1, { MEMORY|BITS8, 0, 0 }, "\x0F\x18", 2, 1, { -1, -1, -1 } },
  { I_PREFETCHT1, 1, { MEMORY|BITS8, 0, 0 }, "\x0F\x18", 2, 2, { -1, -1, -1 } },
  { I_PREFETCHT2, 1, { MEMORY|BITS8, 0, 0 }, "\x0F\x18", 2, 3, { -1, -1, -1 } },
  { I_PSADBW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF6", 2, REGRM, { -1, -1, -1 } },
  { I_PSHUFW, 3, { REG_MMX, MEMORY|BITS64, IMMEDIATE|BITS8 }, "\x0F\x70", 2, REGRM, { -1, -1, -1 } },
  { I_PSLLD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF2", 2, REGRM, { -1, -1, -1 } },
  { I_PSLLD, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x72", 2, 6, { -1, -1, -1 } },
  { I_PSLLQ, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF3", 2, REGRM, { -1, -1, -1 } },
  { I_PSLLQ, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x73", 2, 6, { -1, -1, -1 } },
  { I_PSLLW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF1", 2, REGRM, { -1, -1, -1 } },
  { I_PSLLW, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x71", 2, 6, { -1, -1, -1 } },
  { I_PSRAD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE2", 2, REGRM, { -1, -1, -1 } },
  { I_PSRAD, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x72", 2, 4, { -1, -1, -1 } },
  { I_PSRAW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE1", 2, REGRM, { -1, -1, -1 } },
  { I_PSRAW, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x71", 2, 4, { -1, -1, -1 } },
  { I_PSRLD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD2", 2, REGRM, { -1, -1, -1 } },
  { I_PSRLD, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x72", 2, 2, { -1, -1, -1 } },
  { I_PSRLQ, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD3", 2, REGRM, { -1, -1, -1 } },
  { I_PSRLQ, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x73", 2, 2, { -1, -1, -1 } },
  { I_PSRLW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD1", 2, REGRM, { -1, -1, -1 } },
  { I_PSRLW, 2, { REG_MMX, IMMEDIATE|BITS8, 0 }, "\x0F\x71", 2, 2, { -1, -1, -1 } },
  { I_PSUBB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF8", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xFA", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBSB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE8", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBSW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xE9", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBUSB, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD8", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBUSW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xD9", 2, REGRM, { -1, -1, -1 } },
  { I_PSUBW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xF9", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKHBW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x68", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKHDQ, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x6A", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKHWD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x69", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKLBW, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x60", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKLDQ, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x62", 2, REGRM, { -1, -1, -1 } },
  { I_PUNPCKLWD, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\x61", 2, REGRM, { -1, -1, -1 } },
  { I_PUSH, 1, { REGMEM|BITS16, 0, 0 }, "\xFF", 1, 6, { -1, -1, -1 } },
  { I_PUSH, 1, { REGMEM|BITS32, 0, 0 }, "\xFF", 1, 6, { -1, -1, -1 } },
  { I_PUSH, 1, { REG16, 0, 0 }, "\x50", 1, REGCODE, { -1, -1, -1 } },
  { I_PUSH, 1, { REG32, 0, 0 }, "\x50", 1, REGCODE, { -1, -1, -1 } },
  { I_PUSH, 1, { IMMEDIATE|BITS8, 0, 0 }, "\x6A", 1, -1, { -1, -1, -1 } },
  { I_PUSH, 1, { IMMEDIATE|BITS16, 0, 0 }, "\x68", 1, -1, { -1, -1, -1 } },
  { I_PUSH, 1, { IMMEDIATE|BITS32, 0, 0 }, "\x68", 1, -1, { -1, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x0E", 1, -1, { R_CS, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x16", 1, -1, { R_SS, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x1E", 1, -1, { R_DS, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x06", 1, -1, { R_ES, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x0F\xA0", 2, -1, { R_FS, -1, -1 } },
  { I_PUSH, 1, { REGISTER, 0, 0 }, "\x0F\xA8", 2, -1, { R_GS, -1, -1 } },
  { I_PUSHA, 0, { 0, 0, 0 }, "\x60", 1, -1, { -1, -1, -1 } },
  { I_PUSHAD, 0, { BITS32, 0, 0 }, "\x60", 1, -1, { -1, -1, -1 } },
  { I_PUSHF, 0, { 0, 0, 0 }, "\x9C", 1, -1, { -1, -1, -1 } },
  { I_PUSHFD, 0, { BITS32, 0, 0 }, "\x9C", 1, -1, { -1, -1, -1 } },
  { I_PXOR, 2, { REG_MMX, MEMORY|BITS64, 0 }, "\x0F\xEF", 2, REGRM, { -1, -1, -1 } },
  { I_RCL, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 2, { -1, 1, -1 } },
  { I_RCL, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 2, { -1, R_CL, -1 } },
  { I_RCL, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 2, { -1, -1, -1 } },
  { I_RCL, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 2, { -1, 1, -1 } },
  { I_RCL, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 2, { -1, R_CL, -1 } },
  { I_RCL, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 2, { -1, -1, -1 } },
  { I_RCL, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 2, { -1, 1, -1 } },
  { I_RCL, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 2, { -1, R_CL, -1 } },
  { I_RCL, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 2, { -1, -1, -1 } },
  { I_RCPPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x53", 2, REGRM, { -1, -1, -1 } },
  { I_RCPSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x53", 3, REGRM, { -1, -1, -1 } },
  { I_RCR, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 3, { -1, 1, -1 } },
  { I_RCR, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 3, { -1, R_CL, -1 } },
  { I_RCR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 3, { -1, -1, -1 } },
  { I_RCR, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 3, { -1, 1, -1 } },
  { I_RCR, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 3, { -1, R_CL, -1 } },
  { I_RCR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 3, { -1, -1, -1 } },
  { I_RCR, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 3, { -1, 1, -1 } },
  { I_RCR, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 3, { -1, R_CL, -1 } },
  { I_RCR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 3, { -1, -1, -1 } },
  { I_RDMSR, 0, { 0, 0, 0 }, "\x0F\x32", 2, -1, { -1, -1, -1 } },
  { I_RDPMC, 0, { 0, 0, 0 }, "\x0F\x33", 2, -1, { -1, -1, -1 } },
  { I_RDTSC, 0, { 0, 0, 0 }, "\x0F\x31", 2, -1, { -1, -1, -1 } },
  { I_RETF, 0, { 0, 0, 0 }, "\xCB", 1, -1, { -1, -1, -1 } },
  { I_RETF, 1, { IMMEDIATE|BITS16, 0, 0 }, "\xCA", 1, -1, { -1, -1, -1 } },
  { I_RETN, 0, { 0, 0, 0 }, "\xC3", 1, -1, { -1, -1, -1 } },
  { I_RETN, 1, { IMMEDIATE|BITS16, 0, 0 }, "\xC2", 1, -1, { -1, -1, -1 } },
  { I_ROL, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 0, { -1, 1, -1 } },
  { I_ROL, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 0, { -1, R_CL, -1 } },
  { I_ROL, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 0, { -1, -1, -1 } },
  { I_ROL, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 0, { -1, 1, -1 } },
  { I_ROL, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 0, { -1, R_CL, -1 } },
  { I_ROL, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 0, { -1, -1, -1 } },
  { I_ROL, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 0, { -1, 1, -1 } },
  { I_ROL, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 0, { -1, R_CL, -1 } },
  { I_ROL, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 0, { -1, -1, -1 } },
  { I_ROR, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 1, { -1, 1, -1 } },
  { I_ROR, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 1, { -1, R_CL, -1 } },
  { I_ROR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 1, { -1, -1, -1 } },
  { I_ROR, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 1, { -1, 1, -1 } },
  { I_ROR, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 1, { -1, R_CL, -1 } },
  { I_ROR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 1, { -1, -1, -1 } },
  { I_ROR, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 1, { -1, 1, -1 } },
  { I_ROR, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 1, { -1, R_CL, -1 } },
  { I_ROR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 1, { -1, -1, -1 } },
  { I_RSM, 0, { 0, 0, 0 }, "\x0F\xAA", 2, -1, { -1, -1, -1 } },
  { I_RSQRTPS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\x0F\x52", 2, REGRM, { -1, -1, -1 } },
  { I_RSQRTSS, 2, { REG_XMM, MEMORY|BITS128, 0 }, "\xF3\x0F\x52", 3, REGRM, { -1, -1, -1 } },
  { I_SAHF, 0, { 0, 0, 0 }, "\x9E", 1, -1, { -1, -1, -1 } },
  { I_SAR, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 7, { -1, 1, -1 } },
  { I_SAR, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 7, { -1, R_CL, -1 } },
  { I_SAR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 7, { -1, -1, -1 } },
  { I_SAR, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 7, { -1, 1, -1 } },
  { I_SAR, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 7, { -1, R_CL, -1 } },
  { I_SAR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 7, { -1, -1, -1 } },
  { I_SAR, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 7, { -1, 1, -1 } },
  { I_SAR, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 7, { -1, R_CL, -1 } },
  { I_SAR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 7, { -1, -1, -1 } },
  { I_SBB, 2, { REGISTER, IMMEDIATE|BITS8, 0 }, "\x1C", 1, -1, { R_AL, -1, -1 } },
  { I_SBB, 2, { REGISTER, IMMEDIATE|BITS16, 0 }, "\x1D", 1, -1, { R_AX, -1, -1 } },
  { I_SBB, 2, { REGISTER, IMMEDIATE|BITS32, 0 }, "\x1D", 1, -1, { R_EAX, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\x80", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS16, IMMEDIATE|BITS16, 0 }, "\x81", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS32, IMMEDIATE|BITS32, 0 }, "\x81", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\x83", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\x83", 1, 3, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS8, REG8, 0 }, "\x18", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS16, REG16, 0 }, "\x19", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REGMEM|BITS32, REG32, 0 }, "\x19", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REG8, REGMEM|BITS8, 0 }, "\x1A", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REG16, REGMEM|BITS16, 0 }, "\x1B", 1, REGRM, { -1, -1, -1 } },
  { I_SBB, 2, { REG32, REGMEM|BITS32, 0 }, "\x1B", 1, REGRM, { -1, -1, -1 } },
  { I_SCASB, 0, { 0, 0, 0 }, "\xAE", 1, -1, { -1, -1, -1 } },
  { I_SCASD, 0, { BITS32, 0, 0 }, "\xAF", 1, -1, { -1, -1, -1 } },
  { I_SCASW, 0, { 0, 0, 0 }, "\xAF", 1, -1, { -1, -1, -1 } },
  { I_SETA, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x97", 2, REGRM, { -1, -1, -1 } },
  { I_SETC, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x92", 2, REGRM, { -1, -1, -1 } },
  { I_SETE, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x94", 2, REGRM, { -1, -1, -1 } },
  { I_SETG, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9F", 2, REGRM, { -1, -1, -1 } },
  { I_SETL, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9C", 2, REGRM, { -1, -1, -1 } },
  { I_SETNA, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x96", 2, REGRM, { -1, -1, -1 } },
  { I_SETNC, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x93", 2, REGRM, { -1, -1, -1 } },
  { I_SETNE, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x95", 2, REGRM, { -1, -1, -1 } },
  { I_SETNG, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9E", 2, REGRM, { -1, -1, -1 } },
  { I_SETNL, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9D", 2, REGRM, { -1, -1, -1 } },
  { I_SETNO, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x91", 2, REGRM, { -1, -1, -1 } },
  { I_SETNP, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9B", 2, REGRM, { -1, -1, -1 } },
  { I_SETNS, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x99", 2, REGRM, { -1, -1, -1 } },
  { I_SETO, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x90", 2, REGRM, { -1, -1, -1 } },
  { I_SETP, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x9A", 2, REGRM, { -1, -1, -1 } },
  { I_SETS, 1, { REGMEM|BITS8, 0, 0 }, "\x0F\x98", 2, REGRM, { -1, -1, -1 } },
  { I_SFENCE, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\xAE", 2, 7, { -1, -1, -1 } },
  { I_SGDT, 1, { MEMORY, 0, 0 }, "\x0F\x01", 2, 0, { -1, -1, -1 } },
  { I_SHL, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 4, { -1, 1, -1 } },
  { I_SHL, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 4, { -1, R_CL, -1 } },
  { I_SHL, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 4, { -1, -1, -1 } },
  { I_SHL, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 4, { -1, 1, -1 } },
  { I_SHL, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 4, { -1, R_CL, -1 } },
  { I_SHL, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 4, { -1, -1, -1 } },
  { I_SHL, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 4, { -1, 1, -1 } },
  { I_SHL, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 4, { -1, R_CL, -1 } },
  { I_SHL, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 4, { -1, -1, -1 } },
  { I_SHLD, 3, { REGMEM|BITS16, REG16, IMMEDIATE|BITS8 }, "\x0F\xA4", 2, REGRM, { -1, -1, -1 } },
  { I_SHLD, 3, { REGMEM|BITS16, REG16, REGISTER }, "\x0F\xA5", 2, REGRM, { -1, -1, R_CL } },
  { I_SHLD, 3, { REGMEM|BITS32, REG32, IMMEDIATE|BITS8 }, "\x0F\xA4", 2, REGRM, { -1, -1, -1 } },
  { I_SHLD, 3, { REGMEM|BITS32, REG32, REGISTER }, "\x0F\xA5", 2, REGRM, { -1, -1, R_CL } },
  { I_SHR, 2, { REGMEM|BITS8, CONSTANT, 0 }, "\xD0", 1, 5, { -1, 1, -1 } },
  { I_SHR, 2, { REGMEM|BITS8, REGISTER, 0 }, "\xD2", 1, 5, { -1, R_CL, -1 } },
  { I_SHR, 2, { REGMEM|BITS8, IMMEDIATE|BITS8, 0 }, "\xC0", 1, 5, { -1, -1, -1 } },
  { I_SHR, 2, { REGMEM|BITS16, CONSTANT, 0 }, "\xD1", 1, 5, { -1, 1, -1 } },
  { I_SHR, 2, { REGMEM|BITS16, REGISTER, 0 }, "\xD3", 1, 5, { -1, R_CL, -1 } },
  { I_SHR, 2, { REGMEM|BITS16, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 5, { -1, -1, -1 } },
  { I_SHR, 2, { REGMEM|BITS32, CONSTANT, 0 }, "\xD1", 1, 5, { -1, 1, -1 } },
  { I_SHR, 2, { REGMEM|BITS32, REGISTER, 0 }, "\xD3", 1, 5, { -1, R_CL, -1 } },
  { I_SHR, 2, { REGMEM|BITS32, IMMEDIATE|BITS8, 0 }, "\xC1", 1, 5, { -1, -1, -1 } },
  { I_SHRD, 3, { REGMEM|BITS16, REG16, IMMEDIATE|BITS8 }, "\x0F\xAC", 2, REGRM, { -1, -1, -1 } },
  { I_SHRD, 3, { REGMEM|BITS16, REG16, REGISTER }, "\x0F\xAD", 2, REGRM, { -1, -1, R_CL } },
  { I_SHRD, 3, { REGMEM|BITS32, REG32, IMMEDIATE|BITS8 }, "\x0F\xAC", 2, REGRM, { -1, -1, -1 } },
  { I_SHRD, 3, { REGMEM|BITS32, REG32, REGISTER }, "\x0F\xAD", 2, REGRM, { -1, -1, R_CL } },
  { I_SHUFPS, 3, { REG_XMM, MEMORY|BITS128, IMMEDIATE|BITS8 }, "\x0F\xC6", 2, REGRM, { -1, -1, -1 } },
  { I_SIDT, 1, { MEMORY, 0, 0 }, "\x0F\x01", 2, 1, { -1, -1, -1 } },
  { I_SLDT, 1, { REGMEM|BITS16, 0, 0 }, "\x0F\x00", 2, 0, { -1, -1, -1 } },
  { I_SLDT, 1, { REGMEM|BITS32, 0, 0 }, "\x0F\x00", 2, 0, { -1, -1, -1 } },