wrapper.vhd

浮点fir设计工具

--       AccelDSP 9.1.00 build 868 Production, compiled Feb 16 2007 
-- 
--    THIS IS UNPUBLISHED, LICENSED SOFTWARE THAT IS THE CONFIDENTIAL 
--        AND PROPRIETARY PROPERTY OF XILINX OR ITS LICENSORS 
-- 
--      Copyright(c) Xilinx, Inc., 2000-2007, All Rights Reserved. 
--   Reproduction or reuse, in any form, without the explicit written 
--          consent of Xilinx, Inc., is strictly prohibited. 
-- 
--  User: WangQian 
--  Machine: A2D3DF917F70473 (i1586, Windows XP Service Pack 2, 5.01.2600) 
--  Date: Mon May 12 10:57:37 2008 
-- 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fir is
    port (
		indatabuf : in signed( 11 downto 0 );
		outdatabuf : out signed( 25 downto 0 );
		ac_InputAvail : in std_logic;
		ac_OutputAvail : out std_logic;
		Reset : in std_logic;
		Clock : in std_logic
    );
end fir;

architecture wrapper of fir is
component fir_gates
    port (
		indatabuf : in std_logic_vector( 11 downto 0 );
		outdatabuf : out std_logic_vector( 25 downto 0 );
		ac_InputAvail : in std_logic;
		ac_OutputAvail : out std_logic;
		Reset : in std_logic;
		Clock : in std_logic
    );
end component;
    signal wrapper_indatabuf : std_logic_vector( 11 downto 0 );
    signal wrapper_outdatabuf : std_logic_vector( 25 downto 0 );

begin
    wrapper_indatabuf <= std_logic_vector( indatabuf );
    outdatabuf <= signed( wrapper_outdatabuf );

    wrapper : fir_gates
    port map (
	indatabuf => wrapper_indatabuf,
	outdatabuf => wrapper_outdatabuf,
	ac_InputAvail => ac_InputAvail,
	ac_OutputAvail => ac_OutputAvail,
	Reset => Reset,
	Clock => Clock
    );
end wrapper;