acceldsp_xst_synth_vhdl.opt

浮点fir设计工具

#       AccelDSP 9.1.00 build 868 Production, compiled Feb 16 2007 
# 
#    THIS IS UNPUBLISHED, LICENSED SOFTWARE THAT IS THE CONFIDENTIAL 
#        AND PROPRIETARY PROPERTY OF XILINX OR ITS LICENSORS 
# 
#      Copyright(c) Xilinx, Inc., 2000-2007, All Rights Reserved. 
#   Reproduction or reuse, in any form, without the explicit written 
#          consent of Xilinx, Inc., is strictly prohibited. 
# 
#  User: WangQian 
#  Machine: A2D3DF917F70473 (i1586, Windows XP Service Pack 2, 5.01.2600) 
#  Date: Mon May 12 10:57:37 2008 
# 

FLOWTYPE = FPGA_SYNTHESIS;
Program xst
-ifn <design>_xst.scr;
-ofn acceldsp_XST.log;
ParamFile: <design>_xst.scr
"run";
"-ifn <synthdesign>";
"-ifmt VHDL";
"-ofmt NGC";
"-ofn <design>";
"-p <partname>";
"-opt_mode Speed";
"-opt_level 2";
"-register_balancing YES";
"-iobuf YES";
"-uc C:\AccelDSP\AccelWork\FIR\XST.xcf";
"-write_timing_constraints yes";
"-ent <design>";
End ParamFile
End Program xst