📄 accel_tb_utils.vhd
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-- If data was not read from the line correctly, then it is an indicator
-- that the data is written in a format different from what is expected,
-- such as expecting 4 data elements on the line, but only got 3.
assert read_status
report "Failure to read data correctly from the file: " & filename_fp
severity FAILURE;
if ( cur_data_from_fp_as_integer /= cur_data_from_rtl_as_integer ) then
local_error_cnt := local_error_cnt + 1;
WRITE( error_line, NOW );
WRITE( error_line, string'(": in file " ) );
WRITE( error_line, filename_compare );
WRITE( error_line, string'(": at line " ) );
WRITE( error_line, num_lines_read );
WRITE( error_line, string'( ": Simulation Differences between FixedPoint (" ) );
WRITE( error_line, cur_data_from_fp_as_integer );
WRITE( error_line, string'( ") and RTL (" ) );
WRITE( error_line, cur_data_from_rtl_as_integer );
WRITE( error_line, string'( ")" ) );
WRITELINE( OUTPUT, error_line );
end if;
WRITE( data_line_compare, ' ' );
WRITE( data_line_compare, cur_data_from_fp_as_integer );
WRITE( data_line_compare, ' ' );
WRITE( data_line_compare, cur_data_from_rtl_as_integer );
end loop;
WRITELINE( file_handle_compare_results, data_line_compare );
if ( ENDFILE( file_handle_fixedpoint_results ) ) then
internal_eof <= '1';
file_fixedpoint_opened <= false;
else
internal_eof <= '0';
file_fixedpoint_opened <= true;
end if;
num_lines_written := num_lines_written + 1;
internal_error_cnt <= local_error_cnt + internal_error_cnt;
end if;
end if;
end process WriteCompareData;
Determine_Ack: process ( rst, clk )
begin
if ( rst = '1' ) then
internal_ack <= '1';
if ( output_delay_type = IGNORE_DELAY ) then
delay_cnt <= 0;
delay_value <= 0;
elsif ( output_delay_type = FIXED_DELAY ) then
delay_cnt <= output_delay_amount;
delay_value <= output_delay_amount;
elsif ( output_delay_type = RANDOM_DELAY ) then
assert false
report "Random Delay for setting OutputAck is not supported at this time. Using Constant Delay."
severity WARNING;
delay_cnt <= output_delay_amount;
delay_value <= output_delay_amount;
else
assert false
report "Unknown Delay Type for setting OutputAck for file " & filename_fp & "."
severity FAILURE;
end if;
elsif ( rising_edge(clk) ) then
if ( data_avail = '1' ) then
if ( delay_cnt > 0 ) then
delay_cnt <= delay_cnt - 1;
internal_ack <= '0';
else
delay_cnt <= delay_value;
internal_ack <= '1';
end if;
end if;
end if;
end process Determine_Ack;
cycle_counter: process ( rst, clk )
begin
if ( rst = '1' ) then
cycle_cnt <= 1;
elsif ( rising_edge( clk ) ) then
if ( data_avail = '1' ) then
cycle_cnt <= 1;
else
cycle_cnt <= cycle_cnt + 1;
end if;
end if;
end process cycle_counter;
end architecture beh; --of output_data_handler_unsigned
----------------------------------------------------------------------------------
-- Ouput Data Verifier for Unsigned Types --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.accel_tb_utils.all;
entity output_data_handler_unsigned is
generic ( -- define the generics
filename_tb : string := "";
filename_fp : string := "";
filename_compare : string := "";
precision : integer := 0;
resolution : integer := 0;
num_of_elements : integer := 0;
ram_init_latency : integer := 0;
input_delay_type : integer := 0;
input_delay_amount : integer := 0;
output_delay_type : integer := 0;
output_delay_amount : integer := 0;
push_mode_delay : integer := 16;
dut_sample_rate : integer := 16;
dut_latency : integer := 16
);
port ( rst : in std_logic;
clk : in std_logic;
data_avail : in std_logic; -- when '1', then time to get get data from DUT
data : in unsigned( num_of_elements*(precision+resolution)-1 downto 0 );
data_ack : out std_logic; -- set to '1' when finished processing
end_of_file : out std_logic; -- set to '1' when all data has been compared.
error_cnt : out integer := 0 -- Current tally of number of diffs between FP and RTL
);
end entity output_data_handler_unsigned;
architecture beh of output_data_handler_unsigned is
-- Definitions of sizes of data
constant BIT_WIDTH : integer := precision + resolution;
constant TOTAL_NUM_BITS : integer := num_of_elements*(precision+resolution);
-- File handles
file file_handle_tb : text; -- File that has only results from RTL simulation
file file_handle_compare_results : text; -- File created that has results from RTL Sim and Fixed Point
file file_handle_fixedpoint_results : text; -- File read that has Fixed Point simulation results
-- Flags to know if the files are open
signal file_tb_opened : boolean := false;
signal file_compare_opened : boolean := false;
signal file_fixedpoint_opened : boolean := false;
signal internal_eof : std_logic;
signal internal_error_cnt : integer := 0;
signal internal_ack : std_logic;
signal delay_cnt : integer := 0;
signal delay_value : integer := 0;
signal cycle_cnt : integer := 0;
signal firstPassIsLatency : boolean := true;
begin
-- There are three basic operations that happen when data is received.
-- 1) Data is written to the "_tb.txt" file.
-- 2) Data is compared against expected from FixedPoint Verification
-- 3) Wait the prescribed number of clock cycles before sending the ACK signal
end_of_file <= internal_eof;
error_cnt <= internal_error_cnt;
data_ack <= internal_ack;
WriteOutData: process (rst, clk)
variable file_status : file_open_status;
variable frame_cnt : integer := 0;
variable data_line : line;
variable cur_data_as_integer : integer;
variable cur_frame_of_data : unsigned( BIT_WIDTH-1 downto 0 );
variable num_lines_written : integer := 0;
variable start_bit : integer; -- When working with a Vector of Data, this bit
variable end_bit : integer; -- Bit Positions are the locations the data is placed
-- within the flattened version of the port.
begin
if ( rst = '1' ) then
num_lines_written := 0;
if ( NOT( file_tb_opened ) ) then
FILE_OPEN( file_status, file_handle_tb, filename_tb, WRITE_MODE );
assert (file_status = open_ok)
report "Could not open the output file " & filename_tb & "\ for writing."
severity FAILURE;
file_tb_opened <= true;
end if;
elsif ( rising_edge(clk) ) then
if ( ( data_avail = '1') AND ( delay_cnt = 0 ) ) then
for frame_cnt in num_of_elements-1 downto 0 loop
-- We neof_ed to get the indivitual data elements from the file, and place
-- into a single vector. If there are multiple values, they are placed
-- into the single vector such that the "first" value is placed into the
-- most significant bits, and the "last" value is placed into the
-- least significant bits.
start_bit := TOTAL_NUM_BITS - frame_cnt*BIT_WIDTH - 1;
end_bit := TOTAL_NUM_BITS - (frame_cnt+1)*BIT_WIDTH;
cur_frame_of_data := data( start_bit downto end_bit );
cur_data_as_integer := to_integer( cur_frame_of_data );
WRITE( data_line, cur_data_as_integer );
WRITE( data_line, ' ' );
end loop;
WRITELINE( file_handle_tb, data_line );
num_lines_written := num_lines_written + 1;
end if;
end if;
end process WriteOutData;
WriteCompareData: process (rst, clk)
variable file_status : file_open_status;
variable read_status : boolean;
variable frame_cnt : integer := 0;
-- Various Text I/O Lines used during the comparison operation.
variable data_line_fp : line;
variable data_line_compare : line;
variable error_line : line;
variable cur_data_from_rtl_as_integer : integer;
variable cur_data_from_fp_as_integer : integer;
variable cur_frame_of_data : unsigned( BIT_WIDTH-1 downto 0 );
variable num_lines_written : integer := 0;
variable num_lines_read : integer := 0;
variable local_error_cnt : integer := 0;
variable start_bit : integer; -- When working with a Vector of Data, this bit
variable end_bit : integer; -- Bit Positions are the locations the data is placed
-- within the flattened version of the port.
begin
if ( rst = '1' ) then
internal_error_cnt <= 0;
num_lines_read := 0;
firstPassIsLatency <= true;
if ( NOT( file_compare_opened ) ) then
FILE_OPEN( file_status, file_handle_compare_results, filename_compare, WRITE_MODE );
assert (file_status = open_ok)
report "Could not open the output file " & filename_compare & "\ for writing."
severity FAILURE;
file_compare_opened <= true;
num_lines_written := 0;
WRITE( data_line_compare, NOW );
WRITE( data_line_compare, string'(" reset") ) ;
WRITELINE( file_handle_compare_results, data_line_compare );
end if;
if ( NOT( file_fixedpoint_opened ) ) then
FILE_OPEN( file_status, file_handle_fixedpoint_results, filename_fp, READ_MODE );
assert (file_status = open_ok)
report "Could not open the input file " & filename_fp & "\ for reading."
severity FAILURE;
file_fixedpoint_opened <= true;
num_lines_read := 0;
internal_eof <= '0';
end if;
elsif ( rising_edge(clk) ) then
if ( ( data_avail = '1') AND ( delay_cnt = 0 ) AND ( file_fixedpoint_opened ) ) then
local_error_cnt := 0;
READLINE( file_handle_fixedpoint_results, data_line_fp );
num_lines_read := num_lines_read + 1;
WRITE( data_line_compare, NOW );
WRITE( data_line_compare, ' ' );
if ( firstPassIsLatency ) then
WRITE( data_line_compare, cycle_cnt-ram_init_latency );
firstPassIsLatency <= false;
else
WRITE( data_line_compare, cycle_cnt );
end if;
for frame_cnt in num_of_elements-1 downto 0 loop
-- We need to get the indivitual data elements from the file, and place
-- into a single vector. If there are multiple values, they are placed
-- into the single vector such that the "first" value is placed into the
-- most significant bits, and the "last" value is placed into the
-- least significant bits.
start_bit := TOTAL_NUM_BITS - frame_cnt*BIT_WIDTH - 1;
end_bit := TOTAL_NUM_BITS - (frame_cnt+1)*BIT_WIDTH;
cur_frame_of_data := data( start_bit downto end_bit );
cur_data_from_rtl_as_integer := to_integer( cur_frame_of_data );
READ( data_line_fp, cur_data_from_fp_as_integer, read_status );
-- If data was not read from the line correctly, then it is an indicator
-- that the data is written in a format different from what is expected,
-- such as expecting 4 data elements on the line, but only got 3.
assert read_status
report "Failure to read data correctly from the file: " & filename_fp
severity FAILURE;
if ( cur_data_from_fp_as_integer /= cur_data_from_rtl_as_integer ) then
local_error_cnt := local_error_cnt + 1;
WRITE( error_line, NOW );
WRITE( error_line, string'(": in file " ) );
WRITE( error_line, filename_compare );
WRITE( error_line, string'(": at line " ) );
WRITE( error_line, num_lines_read );
WRITE( error_line, string'( ": Simulation Differences between FixedPoint (" ) );
WRITE( error_line, cur_data_from_fp_as_integer );
WRITE( error_line, string'( ") and RTL (" ) );
WRITE( error_line, cur_data_from_rtl_as_integer );
WRITE( error_line, string'( ")" ) );
WRITELINE( OUTPUT, error_line );
end if;
WRITE( data_line_compare, ' ' );
WRITE( data_line_compare, cur_data_from_fp_as_integer );
WRITE( data_line_compare, ' ' );
WRITE( data_line_compare, cur_data_from_rtl_as_integer );
end loop;
WRITELINE( file_handle_compare_results, data_line_compare );
if ( ENDFILE( file_handle_fixedpoint_results ) ) then
internal_eof <= '1';
file_fixedpoint_opened <= false;
else
internal_eof <= '0';
file_fixedpoint_opened <= true;
end if;
num_lines_written := num_lines_written + 1;
internal_error_cnt <= local_error_cnt + internal_error_cnt;
end if;
end if;
end process WriteCompareData;
Determine_Ack: process ( rst, clk )
begin
if ( rst = '1' ) then
internal_ack <= '1';
if ( output_delay_type = IGNORE_DELAY ) then
delay_cnt <= 0;
delay_value <= 0;
elsif ( output_delay_type = FIXED_DELAY ) then
delay_cnt <= output_delay_amount;
delay_value <= output_delay_amount;
elsif ( output_delay_type = RANDOM_DELAY ) then
assert false
report "Random Delay for setting OutputAck is not supported at this time. Using Constant Delay."
severity WARNING;
delay_cnt <= output_delay_amount;
delay_value <= output_delay_amount;
else
assert false
report "Unknown Delay Type for setting OutputAck for file " & filename_fp & "."
severity FAILURE;
end if;
elsif ( rising_edge(clk) ) then
if ( data_avail = '1' ) then
if ( delay_cnt > 0 ) then
delay_cnt <= delay_cnt - 1;
internal_ack <= '0';
else
delay_cnt <= delay_value;
internal_ack <= '1';
end if;
end if;
end if;
end process Determine_Ack;
cycle_counter: process ( rst, clk )
begin
if ( rst = '1' ) then
cycle_cnt <= 1;
elsif ( rising_edge( clk ) ) then
if ( data_avail = '1' ) then
cycle_cnt <= 1;
else
cycle_cnt <= cycle_cnt + 1;
end if;
end if;
end process cycle_counter;
end architecture beh; --of output_data_handler_unsigned
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