accel_tb_utils.vhd

浮点fir设计工具

--       AccelDSP 9.1.00 build 868 Production, compiled Feb 16 2007 
-- 
--    THIS IS UNPUBLISHED, LICENSED SOFTWARE THAT IS THE CONFIDENTIAL 
--        AND PROPRIETARY PROPERTY OF XILINX OR ITS LICENSORS 
-- 
--      Copyright(c) Xilinx, Inc., 2000-2007, All Rights Reserved. 
--   Reproduction or reuse, in any form, without the explicit written 
--          consent of Xilinx, Inc., is strictly prohibited. 

library ieee;

use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.std_logic_vector;
use ieee.numeric_std.all;

package accel_tb_utils is

-- type operation
constant FIXED_OP	: integer := 0;
constant DELAYED_OP : integer := 1;
constant RANDOM_OP	: integer := 2;

-- delay types
constant IGNORE_DELAY : integer := 0;
constant FIXED_DELAY  : integer := 1;
constant RANDOM_DELAY : integer := 2;

component accel_monitor
  
	generic ( -- define the generics 
			max_errors 		 : integer := 0;
			clock_period 		 : time := 10.000 ns;
			clock_high 		 : time := 5.000 ns;
			clock_low 		 : time := 5.000 ns;
			fixed 		 : integer := 1;
			delayed 		 : integer := 0;
			random_min 		 : integer := 0;
			random_max 		 : integer := 0;
			reset_offset 		 : time := 100 ns;
			input_delay_type 		 : integer := 0;
			input_delay_amount 		 : integer := 0;
			output_delay_type 		 : integer := 0;
			output_delay_amount 		 : integer := 0;
			push_mode_delay 		 : integer := 16;
			dut_sample_rate 		 : integer := 16;
			dut_latency 		 : integer := 16 
			);
	port ( 
			reset    	: out std_logic
			; clock     : out std_logic
			; errors    : in integer
			; eos       : in std_logic
			; min       : out integer
			; max       : out integer
			; iteration : out integer
			);

end component;

component random
  
  generic ( seedOne : positive := 1
          ; seedTwo : positive := 1 );
  port ( delay   : out integer
       ; action  : in  std_logic
       ; min     : in  integer
       ; max     : in  integer
       );

end component;

component input_generator_signed
	generic ( -- define the generics 
			filename 		 : string := "";
			precision 		 : integer := 0;
			resolution 		 : integer := 0;
			num_of_elements 		 : integer := 0;
			input_delay_type 		 : integer := 0;
			input_delay_amount 		 : integer := 0;
			output_delay_type 		 : integer := 0;
			output_delay_amount 		 : integer := 0;
			push_mode_delay 		 : integer := 16;
			dut_sample_rate 		 : integer := 16;
			dut_latency 		 : integer := 16 
			);
	port (	rst : in std_logic;
		clk : in std_logic;
		data_req : in std_logic;		-- when '1', then time to get more data
		data : out signed( num_of_elements*(precision+resolution)-1 downto 0 );
		data_avail : out std_logic;		-- set to '1' when data is ready for reading.
		end_of_file : out std_logic		-- set to '1' when all data has been read.
	     );
end component;

component input_generator_unsigned
	generic ( -- define the generics 
			filename 		 : string := "";
			precision 		 : integer := 0;
			resolution 		 : integer := 0;
			num_of_elements 		 : integer := 0;
			input_delay_type 		 : integer := 0;
			input_delay_amount 		 : integer := 0;
			output_delay_type 		 : integer := 0;
			output_delay_amount 		 : integer := 0;
			push_mode_delay 		 : integer := 16;
			dut_sample_rate 		 : integer := 16;
			dut_latency 		 : integer := 16 
			);
	port (	rst : in std_logic;
		clk : in std_logic;
		data_req : in std_logic;		-- when '1', then time to get more data
		data : out unsigned( num_of_elements*(precision+resolution)-1 downto 0 );
		data_avail : out std_logic;		-- set to '1' when data is ready for reading.
		end_of_file : out std_logic		-- set to '1' when all data has been read.
	     );
end component;

component output_data_handler_signed
	generic ( -- define the generics 
			filename_tb 		 : string := "";
			filename_fp 		 : string := "";
			filename_compare 		 : string := "";
			precision 		 : integer := 0;
			resolution 		 : integer := 0;
			num_of_elements 		 : integer := 0;
			ram_init_latency 		 : integer := 0;
			input_delay_type 		 : integer := 0;
			input_delay_amount 		 : integer := 0;
			output_delay_type 		 : integer := 0;
			output_delay_amount 		 : integer := 0;
			push_mode_delay 		 : integer := 16;
			dut_sample_rate 		 : integer := 16;
			dut_latency 		 : integer := 16 
			);
	port (	rst : in std_logic;
		clk : in std_logic;
		data_avail : in std_logic;		-- when '1', then time to get get data from DUT
		data : in signed( num_of_elements*(precision+resolution)-1 downto 0 );
		data_ack : out std_logic;		-- set to '1' when finished processing
		end_of_file : out std_logic;		-- set to '1' when all data has been compared.
		error_cnt : out integer := 0		-- Current tally of number of diffs between FP and RTL
	     );
end component;

component output_data_handler_unsigned
	generic ( -- define the generics 
			filename_tb 		 : string := "";
			filename_fp 		 : string := "";
			filename_compare 		 : string := "";
			precision 		 : integer := 0;
			resolution 		 : integer := 0;
			num_of_elements 		 : integer := 0;
			ram_init_latency 		 : integer := 0;
			input_delay_type 		 : integer := 0;
			input_delay_amount 		 : integer := 0;
			output_delay_type 		 : integer := 0;
			output_delay_amount 		 : integer := 0;
			push_mode_delay 		 : integer := 16;
			dut_sample_rate 		 : integer := 16;
			dut_latency 		 : integer := 16 
			);
	port (	rst : in std_logic;
		clk : in std_logic;
		data_avail : in std_logic;		-- when '1', then time to get get data from DUT
		data : in unsigned( num_of_elements*(precision+resolution)-1 downto 0 );
		data_ack : out std_logic;		-- set to '1' when finished processing
		end_of_file : out std_logic;		-- set to '1' when all data has been compared.
		error_cnt : out integer := 0		-- Current tally of number of diffs between FP and RTL
	     );
end component;

end accel_tb_utils;


--------------------------------------------------------------------------------------------------------

library std;

use std.textio.all;

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_bit.rising_edge;

library work;
use work.accel_tb_utils.all;

entity accel_monitor is
 
	generic ( -- define the generics 
			max_errors 		 : integer := 0;
			clock_period 		 : time := 10.000 ns;
			clock_high 		 : time := 5.000 ns;
			clock_low 		 : time := 5.000 ns;
			fixed 		 : integer := 1;
			delayed 		 : integer := 0;
			random_min 		 : integer := 0;
			random_max 		 : integer := 0;
			reset_offset 		 : time := 100 ns;
			input_delay_type 		 : integer := 0;
			input_delay_amount 		 : integer := 0;
			output_delay_type 		 : integer := 0;
			output_delay_amount 		 : integer := 0;
			push_mode_delay 		 : integer := 16;
			dut_sample_rate 		 : integer := 16;
			dut_latency 		 : integer := 16 
			);
	port ( 
			reset    	: out std_logic := '0'
			; clock     : out std_logic := '0'
			; errors    : in integer
			; eos       : in std_logic
			; min       : out integer := 0
			; max       : out integer := 0
			; iteration : out integer := FIXED_OP
			);

end accel_monitor;

architecture arch of accel_monitor is

  signal reset_io : std_logic := '0';
  signal clock_io : std_logic := '0';
  signal halt_clock : std_logic := '0';

  signal iteration_io : integer := FIXED_OP;

  signal delta : boolean := false;
  constant POWERUPDELAY : time := 200 ns;

begin

reset <= reset_io;
clock <= clock_io;
iteration <= iteration_io;

resetProcess:
process 
  is
begin

  if fixed /= 0 then
    
    -- fixed iteration

    iteration_io <= FIXED_OP;

    min <= fixed - 1;
    max <= fixed - 1;

    delta <= not delta;

    wait on delta;

    reset_io <= '1';
    wait for POWERUPDELAY;		-- To Allow for FPGA Power-up Routines
    wait for (clock_low + clock_high);
    wait until (clock_io = '1');
    reset_io <= '0' AFTER clock_low/10;
    wait until (clock_io = '0');
    

    wait until eos = '1';

    wait until (clock_io = '1');
    wait until (clock_io = '0');

  end if;

  if delayed /= 0 then
    
    -- delayed iteration

    iteration_io <= DELAYED_OP;

    min <= delayed;
    max <= delayed;

    delta <= not delta;

    wait on delta;

    reset_io <= '1';
    wait for POWERUPDELAY;		-- To Allow for FPGA Power-up Routines
    wait for (clock_low + clock_high);

    wait until (clock_io = '1');
    reset_io <= '0' AFTER clock_low/10;
    wait until (clock_io = '0');


    wait until eos = '1';

  end if;

  if random_min /= 0 or random_max /= 0 then
    
    -- random iteration

    iteration_io <= RANDOM_OP;

    min <= random_min;
    max <= random_max;

    delta <= not delta;

    wait on delta;

    reset_io <= '1';
    wait for POWERUPDELAY;		-- To Allow for FPGA Power-up Routines
    wait for (clock_low + clock_high);

    wait until (clock_io = '1');
    reset_io <= '0' AFTER clock_low/10;
    wait until (clock_io = '0');

    
    wait until eos = '1';

  end if;

  halt_clock <= '1';
  
  wait;

end process ResetProcess;

clockProcess:
process 
  is
begin
  wait for POWERUPDELAY;
  while (true) loop
    Clock_io <= '1' after clock_low;
    wait until (Clock_io = '1');
  
    Clock_io <= '0' after clock_high;
    wait until (Clock_io = '0');

    if halt_clock = '1' then
      wait;
    end if;
  end loop;
  
end process ClockProcess;

init:
process
  variable l : line;
begin
  wait until reset_io = '1';

  write( l, string'( "@ " ) );
  write( l, NOW );
  write( l, string'( " " ) );
  write( l, string'( "beginning simulation" ) );

  if iteration_io = FIXED_OP then
    write( l, string'( " at fixed data rate" ) );
  end if;

  if iteration_io = DELAYED_OP then
    write( l, string'( " at delayed data rate" ) );
  end if;

  if iteration_io = RANDOM_OP then
    write( l, string'( " at random data rate" ) );
  end if;

  writeline( output, l );

  wait until reset_io = '0';

end process;

final:
process
  variable l : line;
begin
  wait until eos = '1';
  write( l, string'( "@ " ) );
  write( l, NOW );
  write( l, string'( " " ) );