generatertlreport.xml

浮点fir设计工具

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<accelrpt>

  <TargetInformationSummary>
    <target>
      <TARGETINFO>
        <Vendor>Xilinx</Vendor>
      </TARGETINFO>
      <TARGETINFO>
        <Family>Virtex-4</Family>
      </TARGETINFO>
      <TARGETINFO>
        <Device>XC4VSX35</Device>
      </TARGETINFO>
      <TARGETINFO>
        <Speed>-12</Speed>
      </TARGETINFO>
      <TARGETINFO>
        <Package>FF668</Package>
      </TARGETINFO>
      <TARGETINFO>
        <IOs>448</IOs>
      </TARGETINFO>
      <TARGETINFO>
        <Frequency>100</Frequency>
      </TARGETINFO>
    </target>
  </TargetInformationSummary>

  <InterfaceSummary>
    <options>
      <register_inputs>
        <REQUESTED>0</REQUESTED>
        <ACTUAL>0</ACTUAL>
        <MISMATCH>0</MISMATCH>
        <WARNINGS></WARNINGS>
      </register_inputs>
      <handshake_mode>
        <REQUESTED>full</REQUESTED>
        <ACTUAL>push</ACTUAL>
        <MISMATCH>1</MISMATCH>
        <WARNINGS></WARNINGS>
      </handshake_mode>
    </options>
    <inport>
      <port>
        <NAME>indatabuf</NAME>
        <WIDTH>12</WIDTH>
      </port>
      <port>
        <NAME>ac_InputAvail</NAME>
        <WIDTH>1</WIDTH>
      </port>
      <port>
        <NAME>Reset</NAME>
        <WIDTH>1</WIDTH>
      </port>
      <port>
        <NAME>Clock</NAME>
        <WIDTH>1</WIDTH>
      </port>
    </inport>
    <outport>
      <port>
        <NAME>outdatabuf</NAME>
        <WIDTH>26</WIDTH>
      </port>
      <port>
        <NAME>ac_OutputAvail</NAME>
        <WIDTH>1</WIDTH>
      </port>
    </outport>
  </InterfaceSummary>

  <ResourceSummary>
    <memory/>
    <resource>
      <RESOURCE>
        <NAME>fir</NAME>
        <DFF>450</DFF>
        <MUL>1</MUL>
        <ADD>1</ADD>
        <AND>0</AND>
        <OR>14</OR>
        <EQEQ>2</EQEQ>
        <NE>0</NE>
        <GT>0</GT>
        <LT>0</LT>
        <GTE>0</GTE>
        <LTE>0</LTE>
        <SUB>0</SUB>
      </RESOURCE>
      <TOTALS>
        <NAME>TOTAL</NAME>
        <DFF>450</DFF>
        <MUL>1</MUL>
        <ADD>1</ADD>
        <AND>0</AND>
        <OR>14</OR>
        <EQEQ>2</EQEQ>
        <NE>0</NE>
        <GT>0</GT>
        <LT>0</LT>
        <GTE>0</GTE>
        <LTE>0</LTE>
        <SUB>0</SUB>
      </TOTALS>
    </resource>
    <netlistapp/>
  </ResourceSummary>

  <PerformanceSummary>
    <timing/>
    <loop/>
    <clock_cycles>
      <values>
        <CONSTANT_THROUGHPUT>1</CONSTANT_THROUGHPUT>
        <THROUGHPUT>16</THROUGHPUT>
        <LATENCY>16</LATENCY>
        <WARNINGS></WARNINGS>
      </values>
    </clock_cycles>
  </PerformanceSummary>

  <FileInformationSummary>
    <verifiles/>
    <vhdlfiles>
      <VHDLFILE>
        <FILENAME>fir.vhd</FILENAME>
      </VHDLFILE>
      <VHDLGATELEVELWRAPPERFILE>
        <FILENAME>wrapper.vhd</FILENAME>
      </VHDLGATELEVELWRAPPERFILE>
      <VHDLTESTBENCHFILE>
        <FILENAME>testbench.vhd</FILENAME>
      </VHDLTESTBENCHFILE>
    </vhdlfiles>
    <inputfiles/>
  </FileInformationSummary>

  <ToolInformationSummary>
    <toolmemory/>
    <GeneralInfo>
      <ElapsedTime>
        <TIME>2.23</TIME>
      </ElapsedTime>
    </GeneralInfo>
  </ToolInformationSummary>

</accelrpt>