toolinfo.tcl

浮点fir设计工具

#       AccelDSP 9.1.00 build 868 Production, compiled Feb 16 2007 
# 
#    THIS IS UNPUBLISHED, LICENSED SOFTWARE THAT IS THE CONFIDENTIAL 
#        AND PROPRIETARY PROPERTY OF XILINX OR ITS LICENSORS 
# 
#      Copyright(c) Xilinx, Inc., 2000-2007, All Rights Reserved. 
#   Reproduction or reuse, in any form, without the explicit written 
#          consent of Xilinx, Inc., is strictly prohibited. 
# 
#  User: WangQian 
#  Machine: A2D3DF917F70473 (i1586, Windows XP Service Pack 2, 5.01.2600) 
#  Date: Mon May 12 10:57:37 2008 
# 
namespace eval ::AccelDSPToolInfo {
	#Return the relative path of file with respect to dir
	proc GetRelativePath {file dir} {
		if { [string length $dir] == 0 } {
			return $file
		}
	
		if { ![string equal [file pathtype $file] absolute] } {
			return $file
		}
	
		if { ![string equal [file pathtype $dir] absolute] } {
			error "GetRelativePath parameter '$dir' not absolute"
		}
	
		set fileSplit [file split $file]
		set dirSplit  [file split $dir]
	
		for { set start 0 } { $start < [llength $fileSplit] && $start < [llength $dirSplit] && [string equal [lindex $fileSplit $start] [lindex $dirSplit $start]]} {incr start} {
		}
	
		set retVal {}
		for {set ii $start} {$ii < [llength $dirSplit]} {incr ii} {
			set retVal [file join $retVal ..]
		}
		
		for {set ii $start} {$ii < [llength $fileSplit]} {incr ii} {
			set retVal [file join $retVal [lindex $fileSplit $ii]]
		}
		return $retVal
	}

	#Substitutes all WINDOWS style slashes with UNIX style
	proc MakeUnixPath { path } {
		regsub -all {\\} $path {/} unixpath
		return $unixpath
	}
	

	variable ProjectDir {C:\AccelDSP\AccelWork\FIR}
	proc GetProjectDir {} { variable ProjectDir; return $ProjectDir }

	variable TBDesignName testbench
	proc GetTBDesignName {} { variable TBDesignName; return $TBDesignName }

	variable DesignName fir
	proc GetDesignName {} { variable DesignName; return $DesignName }

	variable VHDLTestbenchFiles {{{VHDL\testbench.vhd} work}}
	proc GetVHDLTestbenchFiles {} { variable VHDLTestbenchFiles; return $VHDLTestbenchFiles }

	variable VerilogTestbenchFiles {}
	proc GetVerilogTestbenchFiles {} { variable VerilogTestbenchFiles; return $VerilogTestbenchFiles }

	variable VHDLWrapperFiles {{{VHDL\wrapper.vhd} work}}
	proc GetVHDLWrapperFiles {} { variable VHDLWrapperFiles; return $VHDLWrapperFiles }

	variable VerilogWrapperFiles {}
	proc GetVerilogWrapperFiles {} { variable VerilogWrapperFiles; return $VerilogWrapperFiles }

	variable VHDLDesignFiles {{{VHDL\fir.vhd} work}}
	proc GetVHDLDesignFiles {} { variable VHDLDesignFiles; return $VHDLDesignFiles }

	variable VHDLEntity fir
	proc GetVHDLEntity {} { variable VHDLEntity; return $VHDLEntity }

	variable VerilogDesignFiles {}
	proc GetVerilogDesignFiles {} { variable VerilogDesignFiles; return $VerilogDesignFiles }

	variable VerilogModule {{}}
	proc GetVerilogModule {} { variable VerilogModule; return $VerilogModule }

	variable FixedPointMDesignFiles {{{FixedPointM\fir_script.m} work} {{FixedPointM\fir.m} work} {{FixedPointM\mtimes_001.m} work}}
	proc GetFixedPointMDesignFiles {} { variable FixedPointMDesignFiles; return $FixedPointMDesignFiles }

	variable FixedPointMModule mtimes_001
	proc GetFixedPointMModule {} { variable FixedPointMModule; return $FixedPointMModule }

	variable FixedPointCDesignFiles {{{FixedPointC\fir_script.m} work} {{FixedPointC\AccelCommon.h} work} {{FixedPointC\fir.h} work} {{FixedPointC\fir_mex.cpp} work} {{FixedPointC\fir.dll} work} {{FixedPointC\mtimes_001.cpp} work} {{FixedPointC\fir.cpp} work}}
	proc GetFixedPointCDesignFiles {} { variable FixedPointCDesignFiles; return $FixedPointCDesignFiles }

	variable FixedPointCModule fir
	proc GetFixedPointCModule {} { variable FixedPointCModule; return $FixedPointCModule }

	variable MatlabElaboratedDesignFiles {}
	proc GetMatlabElaboratedDesignFiles {} { variable MatlabElaboratedDesignFiles; return $MatlabElaboratedDesignFiles }

	variable MatlabElaboratedModule {{}}
	proc GetMatlabElaboratedModule {} { variable MatlabElaboratedModule; return $MatlabElaboratedModule }

	variable SimulinkDesignFiles {}
	proc GetSimulinkDesignFiles {} { variable SimulinkDesignFiles; return $SimulinkDesignFiles }

	variable SimulinkModule {{}}
	proc GetSimulinkModule {} { variable SimulinkModule; return $SimulinkModule }

	variable NonVHDLDesignFiles {}
	proc GetNonVHDLDesignFiles {} { variable NonVHDLDesignFiles; return $NonVHDLDesignFiles }

	variable NonVerilogDesignFiles {}
	proc GetNonVerilogDesignFiles {} { variable NonVerilogDesignFiles; return $NonVerilogDesignFiles }

	variable VHDLSimulationLibFiles {{{VHDL\lib\accel_tb_utils.vhd} work}}
	proc GetVHDLSimulationLibFiles {} { variable VHDLSimulationLibFiles; return $VHDLSimulationLibFiles }

	variable VerilogSimulationLibFiles {}
	proc GetVerilogSimulationLibFiles {} { variable VerilogSimulationLibFiles; return $VerilogSimulationLibFiles }

	variable Vendor Xilinx
	proc GetVendor {} { variable Vendor; return $Vendor }

	variable Family Virtex-4
	proc GetFamily {} { variable Family; return $Family }

	variable Device XC4VSX35
	proc GetDevice {} { variable Device; return $Device }

	variable Speed -12
	proc GetSpeed {} { variable Speed; return $Speed }

	variable Package FF668
	proc GetPackage {} { variable Package; return $Package }

	variable IOs 448
	proc GetIOs {} { variable IOs; return $IOs }

	variable Frequency 100
	proc GetFrequency {} { variable Frequency; return $Frequency }

}