rst_gen.v

filter,很不错,大家可以看以下

module clk_div(clk_i,clk_4);

input  clk_i;
output clk_4;

reg[1:0] Cnt=0;


always @(posedge clk_i)
begin
     Cnt<=Cnt+1;
 end

assign clk_4 = Cnt[1];

endmodule