reset_gen.v

filter,很不错,大家可以看以下

module reset_gen(
	clk,
	rst_in,
	rst_out
	);
	
input	clk;
input	rst_in;

output	rst_out;

reg	[23:0]	rst_cnt;
always @ (posedge clk or negedge rst_in)
if(!rst_in)
	rst_cnt <= 1'b0;
else if(!rst_cnt[23])
	rst_cnt <= rst_cnt + 1'b1;

wire	rst_out = rst_cnt[23];
endmodule