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📄 altsyncram_rvm2.tdf

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			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 49,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 49,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a50 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 50,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 50,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a51 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 51,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 51,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a52 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 52,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 52,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a53 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 53,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 53,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a54 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 54,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 54,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a55 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 55,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 55,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a56 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 56,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 56,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a57 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 57,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 57,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a58 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 58,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 58,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a59 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 59,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 59,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a60 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 60,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 60,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a61 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "none",
			INIT_FILE_LAYOUT = "port_b",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 61,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 115,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 61,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 115,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a62 : cyclone
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