i2c_altera.hier_info

filter,很不错,大家可以看以下

rst => row_cnt[0].ACLR
rst => row_cnt[9].ACLR
rst => byte_cnt[0].ACLR
rst => byte_cnt[1].ACLR
rst => add_mask_ena.ACLR
rst => r_ram_rab[12].ACLR
rst => r_ram_rab[11].ACLR
rst => r_ram_rab[10].ACLR
rst => r_ram_rab[9].ACLR
rst => r_ram_rab[8].ACLR
rst => r_ram_rab[7].ACLR
rst => r_ram_rab[6].ACLR
rst => r_ram_rab[5].ACLR
rst => r_ram_rab[4].ACLR
rst => r_ram_rab[3].ACLR
rst => r_ram_rab[2].ACLR
rst => r_ram_rab[1].ACLR
rst => r_ram_rab[0].ACLR
rst => r_ram_rab[13].ACLR
rst => data4byte[30].ACLR
rst => data4byte[29].ACLR
rst => data4byte[28].ACLR
rst => data4byte[27].ACLR
rst => data4byte[26].ACLR
rst => data4byte[25].ACLR
rst => data4byte[24].ACLR
rst => data4byte[23].ACLR
rst => data4byte[22].ACLR
rst => data4byte[21].ACLR
rst => data4byte[20].ACLR
rst => data4byte[19].ACLR
rst => data4byte[18].ACLR
rst => data4byte[17].ACLR
rst => data4byte[16].ACLR
rst => data4byte[15].ACLR
rst => data4byte[14].ACLR
rst => data4byte[13].ACLR
rst => data4byte[12].ACLR
rst => data4byte[11].ACLR
rst => data4byte[10].ACLR
rst => data4byte[9].ACLR
rst => data4byte[8].ACLR
rst => data4byte[7].ACLR
rst => data4byte[6].ACLR
rst => data4byte[5].ACLR
rst => data4byte[4].ACLR
rst => data4byte[3].ACLR
rst => data4byte[2].ACLR
rst => data4byte[1].ACLR
rst => data4byte[0].ACLR
rst => data4byte[31].ACLR
rst => byte_cnt_out[0].ACLR
rst => byte_cnt_out[1].ACLR
rst => STATE~4.IN1
clk => clk~0.IN1
qd[0] => qd_dly[0].DATAIN
qd[1] => qd_dly[1].DATAIN
qd[2] => qd_dly[2].DATAIN
qd[3] => qd_dly[3].DATAIN
qd[4] => qd_dly[4].DATAIN
qd[5] => qd_dly[5].DATAIN
qd[6] => qd_dly[6].DATAIN
qd[7] => qd_dly[7].DATAIN
qfv_odd => qfv_dly~0.IN1
qfv_odd => Select~1.IN2
qfv_odd => Select~2.IN4
qfv_even => qfv_dly~0.IN0
qfv_even => Select~2.IN1
qfv_even => STATE~2.DATAB
qd_out[0] <= qd_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qd_out[1] <= qd_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qd_out[2] <= qd_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qd_out[3] <= qd_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qd_out[4] <= qd_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qd_out[5] <= qd_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qd_out[6] <= qd_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qd_out[7] <= qd_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qfv_out <= qfv_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|add_mask:inst22|mask_rom:mask_rom0
address[0] => address[0]~13.IN1
address[1] => address[1]~12.IN1
address[2] => address[2]~11.IN1
address[3] => address[3]~10.IN1
address[4] => address[4]~9.IN1
address[5] => address[5]~8.IN1
address[6] => address[6]~7.IN1
address[7] => address[7]~6.IN1
address[8] => address[8]~5.IN1
address[9] => address[9]~4.IN1
address[10] => address[10]~3.IN1
address[11] => address[11]~2.IN1
address[12] => address[12]~1.IN1
address[13] => address[13]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a


|I2C_ALTERA|add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_j1t:auto_generated.address_a[0]
address_a[1] => altsyncram_j1t:auto_generated.address_a[1]
address_a[2] => altsyncram_j1t:auto_generated.address_a[2]
address_a[3] => altsyncram_j1t:auto_generated.address_a[3]
address_a[4] => altsyncram_j1t:auto_generated.address_a[4]
address_a[5] => altsyncram_j1t:auto_generated.address_a[5]
address_a[6] => altsyncram_j1t:auto_generated.address_a[6]
address_a[7] => altsyncram_j1t:auto_generated.address_a[7]
address_a[8] => altsyncram_j1t:auto_generated.address_a[8]
address_a[9] => altsyncram_j1t:auto_generated.address_a[9]
address_a[10] => altsyncram_j1t:auto_generated.address_a[10]
address_a[11] => altsyncram_j1t:auto_generated.address_a[11]
address_a[12] => altsyncram_j1t:auto_generated.address_a[12]
address_a[13] => altsyncram_j1t:auto_generated.address_a[13]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_j1t:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_j1t:auto_generated.q_a[0]
q_b[0] <= <GND>


|I2C_ALTERA|add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[12] => address_reg_a[0].DATAIN
address_a[12] => decode_iga:deep_decode.data[0]
address_a[13] => address_reg_a[1].DATAIN
address_a[13] => decode_iga:deep_decode.data[1]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => address_reg_a[1].CLK
clock0 => address_reg_a[0].CLK
q_a[0] <= mux_rab:mux2.result[0]


|I2C_ALTERA|add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|decode_iga:deep_decode
data[0] => w_anode38w[1].IN1
data[0] => w_anode54w[1].IN1
data[1] => w_anode46w[2].IN1
data[1] => w_anode54w[2].IN1
enable => w_anode25w[1].IN0
enable => w_anode38w[1].IN0
enable => w_anode46w[1].IN0
enable => w_anode54w[1].IN0
eq[0] <= w_anode25w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode38w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode46w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode54w[2].DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2
result[0] <= w_result42w.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|reset_gen:inst21
clk => rst_cnt[22].CLK
clk => rst_cnt[21].CLK
clk => rst_cnt[20].CLK
clk => rst_cnt[19].CLK
clk => rst_cnt[18].CLK
clk => rst_cnt[17].CLK
clk => rst_cnt[16].CLK
clk => rst_cnt[15].CLK
clk => rst_cnt[14].CLK
clk => rst_cnt[13].CLK
clk => rst_cnt[12].CLK
clk => rst_cnt[11].CLK
clk => rst_cnt[10].CLK
clk => rst_cnt[9].CLK
clk => rst_cnt[8].CLK
clk => rst_cnt[7].CLK
clk => rst_cnt[6].CLK
clk => rst_cnt[5].CLK
clk => rst_cnt[4].CLK
clk => rst_cnt[3].CLK
clk => rst_cnt[2].CLK
clk => rst_cnt[1].CLK
clk => rst_cnt[0].CLK
clk => rst_cnt[23].CLK
rst_in => rst_cnt[22].ACLR
rst_in => rst_cnt[21].ACLR
rst_in => rst_cnt[20].ACLR
rst_in => rst_cnt[19].ACLR
rst_in => rst_cnt[18].ACLR
rst_in => rst_cnt[17].ACLR
rst_in => rst_cnt[16].ACLR
rst_in => rst_cnt[15].ACLR
rst_in => rst_cnt[14].ACLR
rst_in => rst_cnt[13].ACLR
rst_in => rst_cnt[12].ACLR
rst_in => rst_cnt[11].ACLR
rst_in => rst_cnt[10].ACLR
rst_in => rst_cnt[9].ACLR
rst_in => rst_cnt[8].ACLR
rst_in => rst_cnt[7].ACLR
rst_in => rst_cnt[6].ACLR
rst_in => rst_cnt[5].ACLR
rst_in => rst_cnt[4].ACLR
rst_in => rst_cnt[3].ACLR
rst_in => rst_cnt[2].ACLR
rst_in => rst_cnt[1].ACLR
rst_in => rst_cnt[0].ACLR
rst_in => rst_cnt[23].ACLR
rst_out <= rst_cnt[23].DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|receiver:inst18
rst => qfv_cnt[9].ACLR
rst => qfv_cnt[8].ACLR
rst => qfv_cnt[7].ACLR
rst => qfv_cnt[6].ACLR
rst => qfv_cnt[5].ACLR
rst => qfv_cnt[4].ACLR
rst => qfv_cnt[3].ACLR
rst => qfv_cnt[2].ACLR
rst => qfv_cnt[1].ACLR
rst => qfv_cnt[0].ACLR
rst => qfv_even~reg0.ACLR
rst => qfv_cnt[10].ACLR
rst => qfv_odd~reg0.ACLR
rst => ODD_STATE[1]~reg0.ACLR
rst => ODD_STATE[0]~reg0.ACLR
rst => ODD_STATE[2]~reg0.ACLR
qd[0] => qd_dly[0].DATAIN
qd[1] => qd_dly[1].DATAIN
qd[2] => qd_dly[2].DATAIN
qd[3] => qd_dly[3].DATAIN
qd[4] => qd_dly[4].DATAIN
qd[5] => qd_dly[5].DATAIN
qd[6] => qd_dly[6].DATAIN
qd[7] => qd_dly[7].DATAIN
clk => qd_dly[6].CLK
clk => qd_dly[5].CLK
clk => qd_dly[4].CLK
clk => qd_dly[3].CLK
clk => qd_dly[2].CLK
clk => qd_dly[1].CLK
clk => qd_dly[0].CLK
clk => qd_dly1[7].CLK
clk => qd_dly1[6].CLK
clk => qd_dly1[5].CLK
clk => qd_dly1[4].CLK
clk => qd_dly1[3].CLK
clk => qd_dly1[2].CLK
clk => qd_dly1[1].CLK
clk => qd_dly1[0].CLK
clk => ODD_STATE[2]~reg0.CLK
clk => ODD_STATE[1]~reg0.CLK
clk => ODD_STATE[0]~reg0.CLK
clk => qfv_odd~reg0.CLK
clk => qfv_even~reg0.CLK
clk => qfv_cnt[10].CLK
clk => qfv_cnt[9].CLK
clk => qfv_cnt[8].CLK
clk => qfv_cnt[7].CLK
clk => qfv_cnt[6].CLK
clk => qfv_cnt[5].CLK
clk => qfv_cnt[4].CLK
clk => qfv_cnt[3].CLK
clk => qfv_cnt[2].CLK
clk => qfv_cnt[1].CLK
clk => qfv_cnt[0].CLK
clk => qd_dly[7].CLK
qd_out[0] <= comb~8.DB_MAX_OUTPUT_PORT_TYPE
qd_out[1] <= comb~7.DB_MAX_OUTPUT_PORT_TYPE
qd_out[2] <= comb~6.DB_MAX_OUTPUT_PORT_TYPE
qd_out[3] <= comb~5.DB_MAX_OUTPUT_PORT_TYPE
qd_out[4] <= comb~4.DB_MAX_OUTPUT_PORT_TYPE
qd_out[5] <= comb~3.DB_MAX_OUTPUT_PORT_TYPE
qd_out[6] <= comb~2.DB_MAX_OUTPUT_PORT_TYPE
qd_out[7] <= comb~1.DB_MAX_OUTPUT_PORT_TYPE
qfv <= comb~0.DB_MAX_OUTPUT_PORT_TYPE
qfv_odd <= qfv_odd~reg0.DB_MAX_OUTPUT_PORT_TYPE
qfv_even <= qfv_even~reg0.DB_MAX_OUTPUT_PORT_TYPE
ODD_STATE[0] <= ODD_STATE[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ODD_STATE[1] <= ODD_STATE[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ODD_STATE[2] <= ODD_STATE[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|Led_run:inst14
rst => Mega_cnt[22].ACLR
rst => Mega_cnt[21].ACLR
rst => Mega_cnt[20].ACLR
rst => Mega_cnt[19].ACLR
rst => Mega_cnt[18].ACLR
rst => Mega_cnt[17].ACLR
rst => Mega_cnt[16].ACLR
rst => Mega_cnt[15].ACLR
rst => Mega_cnt[14].ACLR
rst => Mega_cnt[13].ACLR
rst => Mega_cnt[12].ACLR
rst => Mega_cnt[11].ACLR
rst => Mega_cnt[10].ACLR
rst => Mega_cnt[9].ACLR
rst => Mega_cnt[8].ACLR
rst => Mega_cnt[7].ACLR
rst => Mega_cnt[6].ACLR
rst => Mega_cnt[5].ACLR
rst => Mega_cnt[4].ACLR
rst => Mega_cnt[3].ACLR
rst => Mega_cnt[2].ACLR
rst => Mega_cnt[1].ACLR
rst => Mega_cnt[0].ACLR
rst => led[2]~reg0.ACLR
rst => Mega_cnt[23].ACLR
rst => led[1]~reg0.PRESET
rst => led[0]~reg0.ACLR
rst => dir.ACLR
rst => led[3]~reg0.ACLR
clk => Mega_cnt[22].CLK
clk => Mega_cnt[21].CLK
clk => Mega_cnt[20].CLK
clk => Mega_cnt[19].CLK
clk => Mega_cnt[18].CLK
clk => Mega_cnt[17].CLK
clk => Mega_cnt[16].CLK
clk => Mega_cnt[15].CLK
clk => Mega_cnt[14].CLK
clk => Mega_cnt[13].CLK
clk => Mega_cnt[12].CLK
clk => Mega_cnt[11].CLK
clk => Mega_cnt[10].CLK
clk => Mega_cnt[9].CLK
clk => Mega_cnt[8].CLK
clk => Mega_cnt[7].CLK
clk => Mega_cnt[6].CLK
clk => Mega_cnt[5].CLK
clk => Mega_cnt[4].CLK
clk => Mega_cnt[3].CLK
clk => Mega_cnt[2].CLK
clk => Mega_cnt[1].CLK
clk => Mega_cnt[0].CLK
clk => Mega_cnt[23].CLK
led[0] <= led[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led[1] <= led[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led[2] <= led[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led[3] <= led[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE