i2c_altera.hier_info

filter,很不错,大家可以看以下

aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_xnode.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_xnode.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator
dataa[0] => cmpchain:cmp_end.dataa[0]
dataa[1] => cmpchain:cmp_end.dataa[1]
dataa[2] => cmpchain:cmp_end.dataa[2]
dataa[3] => cmpchain:cmp_end.dataa[3]
dataa[4] => cmpchain:cmp_end.dataa[4]
datab[0] => cmpchain:cmp_end.datab[0]
datab[1] => cmpchain:cmp_end.datab[1]
datab[2] => cmpchain:cmp_end.datab[2]
datab[3] => cmpchain:cmp_end.datab[3]
datab[4] => cmpchain:cmp_end.datab[4]
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= cmpchain:cmp_end.aeb
agb <= <GND>


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator|cmpchain:cmp_end
dataa[0] => comptree:comp.dataa[0]
dataa[1] => comptree:comp.dataa[1]
dataa[2] => comptree:comp.dataa[2]
dataa[3] => comptree:comp.dataa[3]
dataa[4] => comptree:comp.dataa[4]
datab[0] => comptree:comp.datab[0]
datab[1] => comptree:comp.datab[1]
datab[2] => comptree:comp.datab[2]
datab[3] => comptree:comp.datab[3]
datab[4] => comptree:comp.datab[4]
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator|cmpchain:cmp_end|comptree:comp
dataa[0] => cmpchain:cmp[0].dataa[0]
dataa[1] => cmpchain:cmp[0].dataa[1]
dataa[2] => cmpchain:cmp[0].dataa[2]
dataa[3] => cmpchain:cmp[0].dataa[3]
dataa[4] => cmpchain:cmp_end.dataa[0]
datab[0] => cmpchain:cmp[0].datab[0]
datab[1] => cmpchain:cmp[0].datab[1]
datab[2] => cmpchain:cmp[0].datab[2]
datab[3] => cmpchain:cmp[0].datab[3]
datab[4] => cmpchain:cmp_end.datab[0]
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_node.DB_MAX_OUTPUT_PORT_TYPE
agb <= <GND>


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[0]
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp_end
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree
dataa[0] => cmpchain:cmp_end.dataa[0]
dataa[1] => cmpchain:cmp_end.dataa[1]
datab[0] => cmpchain:cmp_end.datab[0]
datab[1] => cmpchain:cmp_end.datab[1]
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= cmpchain:cmp_end.aeb
agb <= <GND>


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end
clk => ~NO_FANOUT~
aset => ~NO_FANOUT~
clken => ~NO_FANOUT~
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002|altshift:aeb_ext_lat_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002|altshift:agb_ext_lat_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|i2c_cmd_7128:inst17
clk => cmd_stop~reg0.CLK
clk => cmd_start~reg0.CLK
clk => cmd_send~reg0.CLK
clk => execute~reg0.CLK
clk => rom_addr[6]~reg0.CLK
clk => rom_addr[5]~reg0.CLK
clk => rom_addr[4]~reg0.CLK
clk => rom_addr[3]~reg0.CLK
clk => rom_addr[2]~reg0.CLK
clk => rom_addr[1]~reg0.CLK
clk => rom_addr[0]~reg0.CLK
clk => i2c_data_t[7]~reg0.CLK
clk => i2c_data_t[6]~reg0.CLK
clk => i2c_data_t[5]~reg0.CLK
clk => i2c_data_t[4]~reg0.CLK
clk => i2c_data_t[3]~reg0.CLK
clk => i2c_data_t[2]~reg0.CLK
clk => i2c_data_t[1]~reg0.CLK
clk => i2c_data_t[0]~reg0.CLK
clk => group_index.CLK
clk => i2c_w_finish~reg0.CLK
clk => STATE~13.IN1
rst => STATE~3.OUTPUTSELECT
rst => STATE~4.OUTPUTSELECT
rst => STATE~5.OUTPUTSELECT
rst => STATE~6.OUTPUTSELECT
rst => STATE~7.OUTPUTSELECT
rst => STATE~8.OUTPUTSELECT
rst => STATE~9.OUTPUTSELECT
rst => STATE~10.OUTPUTSELECT
rst => STATE~11.OUTPUTSELECT
rst => STATE~12.OUTPUTSELECT
rst => cmd_stop~0.OUTPUTSELECT
rst => cmd_start~0.OUTPUTSELECT
rst => cmd_send~2.OUTPUTSELECT
rst => execute~0.OUTPUTSELECT
rst => rom_addr~14.OUTPUTSELECT
rst => rom_addr~15.OUTPUTSELECT
rst => rom_addr~16.OUTPUTSELECT
rst => rom_addr~17.OUTPUTSELECT
rst => rom_addr~18.OUTPUTSELECT
rst => rom_addr~19.OUTPUTSELECT
rst => rom_addr~20.OUTPUTSELECT
rst => i2c_data_t~1.OUTPUTSELECT
rst => i2c_data_t~2.OUTPUTSELECT
rst => i2c_data_t~3.OUTPUTSELECT
rst => i2c_data_t~4.OUTPUTSELECT
rst => i2c_data_t~5.OUTPUTSELECT
rst => i2c_data_t~6.OUTPUTSELECT
rst => i2c_data_t~7.OUTPUTSELECT
rst => i2c_data_t~8.OUTPUTSELECT
rst => group_index~2.OUTPUTSELECT
rst => i2c_w_finish~1.OUTPUTSELECT
rst => STATE.IDLE.DATAIN
rom_data[0] => Select~16.IN1
rom_data[1] => Select~15.IN2
rom_data[2] => Select~14.IN1
rom_data[3] => Select~13.IN2
rom_data[4] => Select~12.IN1
rom_data[5] => Select~11.IN1
rom_data[6] => Select~10.IN1
rom_data[7] => Select~9.IN2
busy => Select~7.IN1
busy => Select~5.IN1
busy => Select~3.IN1
busy => Select~1.IN1
busy => STATE~0.OUTPUTSELECT
busy => STATE~2.DATAB
busy => STATE~1.OUTPUTSELECT
busy => rom_addr~7.OUTPUTSELECT
busy => rom_addr~8.OUTPUTSELECT
busy => rom_addr~9.OUTPUTSELECT
busy => rom_addr~10.OUTPUTSELECT
busy => rom_addr~11.OUTPUTSELECT
busy => rom_addr~12.OUTPUTSELECT
busy => rom_addr~13.OUTPUTSELECT
busy => Select~2.IN3
busy => Select~4.IN4
busy => Select~4.IN5
busy => Select~6.IN3
busy => Select~8.IN5
rom_addr[0] <= rom_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[1] <= rom_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[2] <= rom_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[3] <= rom_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[4] <= rom_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[5] <= rom_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[6] <= rom_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[0] <= i2c_data_t[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[1] <= i2c_data_t[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[2] <= i2c_data_t[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[3] <= i2c_data_t[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[4] <= i2c_data_t[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[5] <= i2c_data_t[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[6] <= i2c_data_t[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[7] <= i2c_data_t[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_stop <= cmd_stop~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_start <= cmd_start~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_send <= cmd_send~reg0.DB_MAX_OUTPUT_PORT_TYPE
execute <= execute~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_w_finish <= i2c_w_finish~reg0.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|ENC_ROM:inst16
address[0] => address[0]~6.IN1
address[1] => address[1]~5.IN1
address[2] => address[2]~4.IN1
address[3] => address[3]~3.IN1
address[4] => address[4]~2.IN1
address[5] => address[5]~1.IN1
address[6] => address[6]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|I2C_ALTERA|ENC_ROM:inst16|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_slr:auto_generated.address_a[0]
address_a[1] => altsyncram_slr:auto_generated.address_a[1]
address_a[2] => altsyncram_slr:auto_generated.address_a[2]
address_a[3] => altsyncram_slr:auto_generated.address_a[3]
address_a[4] => altsyncram_slr:auto_generated.address_a[4]
address_a[5] => altsyncram_slr:auto_generated.address_a[5]
address_a[6] => altsyncram_slr:auto_generated.address_a[6]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_slr:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_slr:auto_generated.q_a[0]
q_a[1] <= altsyncram_slr:auto_generated.q_a[1]
q_a[2] <= altsyncram_slr:auto_generated.q_a[2]
q_a[3] <= altsyncram_slr:auto_generated.q_a[3]
q_a[4] <= altsyncram_slr:auto_generated.q_a[4]
q_a[5] <= altsyncram_slr:auto_generated.q_a[5]
q_a[6] <= altsyncram_slr:auto_generated.q_a[6]
q_a[7] <= altsyncram_slr:auto_generated.q_a[7]
q_b[0] <= <GND>


|I2C_ALTERA|ENC_ROM:inst16|altsyncram:altsyncram_component|altsyncram_slr:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|I2C_ALTERA|add_mask:inst22
rst => data4byte_pre[30].ACLR
rst => data4byte_pre[29].ACLR
rst => data4byte_pre[28].ACLR
rst => data4byte_pre[27].ACLR
rst => data4byte_pre[26].ACLR
rst => data4byte_pre[25].ACLR
rst => data4byte_pre[24].ACLR
rst => data4byte_pre[23].ACLR
rst => data4byte_pre[22].ACLR
rst => data4byte_pre[21].ACLR
rst => data4byte_pre[20].ACLR
rst => data4byte_pre[19].ACLR
rst => data4byte_pre[18].ACLR
rst => data4byte_pre[17].ACLR
rst => data4byte_pre[16].ACLR
rst => data4byte_pre[15].ACLR
rst => data4byte_pre[14].ACLR
rst => data4byte_pre[13].ACLR
rst => data4byte_pre[12].ACLR
rst => data4byte_pre[11].ACLR
rst => data4byte_pre[10].ACLR
rst => data4byte_pre[9].ACLR
rst => data4byte_pre[8].ACLR
rst => data4byte_pre[7].ACLR
rst => data4byte_pre[6].ACLR
rst => data4byte_pre[5].ACLR
rst => data4byte_pre[4].ACLR
rst => data4byte_pre[3].ACLR
rst => data4byte_pre[2].ACLR
rst => data4byte_pre[1].ACLR
rst => data4byte_pre[0].ACLR
rst => qd_out[6]~reg0.ACLR
rst => data4byte_pre[31].ACLR
rst => qd_out[5]~reg0.ACLR
rst => qd_out[4]~reg0.ACLR
rst => qd_out[3]~reg0.ACLR
rst => qd_out[2]~reg0.ACLR
rst => qd_out[1]~reg0.ACLR
rst => qd_out[0]~reg0.ACLR
rst => qd_out[7]~reg0.ACLR
rst => row_cnt[8].ACLR
rst => row_cnt[7].ACLR
rst => row_cnt[6].ACLR
rst => row_cnt[5].ACLR
rst => row_cnt[4].ACLR
rst => row_cnt[3].ACLR
rst => row_cnt[2].ACLR
rst => row_cnt[1].ACLR