i2c_altera.hier_info

filter,很不错,大家可以看以下

rst_out <= rst_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|i2c_cmd:inst
clk => cmd_stop~reg0.CLK
clk => cmd_start~reg0.CLK
clk => cmd_send~reg0.CLK
clk => execute~reg0.CLK
clk => rom_addr[6]~reg0.CLK
clk => rom_addr[5]~reg0.CLK
clk => rom_addr[4]~reg0.CLK
clk => rom_addr[3]~reg0.CLK
clk => rom_addr[2]~reg0.CLK
clk => rom_addr[1]~reg0.CLK
clk => rom_addr[0]~reg0.CLK
clk => i2c_data_t[7]~reg0.CLK
clk => i2c_data_t[6]~reg0.CLK
clk => i2c_data_t[5]~reg0.CLK
clk => i2c_data_t[4]~reg0.CLK
clk => i2c_data_t[3]~reg0.CLK
clk => i2c_data_t[2]~reg0.CLK
clk => i2c_data_t[1]~reg0.CLK
clk => i2c_data_t[0]~reg0.CLK
clk => group_index.CLK
clk => i2c_w_finish~reg0.CLK
clk => STATE~13.IN1
rst => STATE~3.OUTPUTSELECT
rst => STATE~4.OUTPUTSELECT
rst => STATE~5.OUTPUTSELECT
rst => STATE~6.OUTPUTSELECT
rst => STATE~7.OUTPUTSELECT
rst => STATE~8.OUTPUTSELECT
rst => STATE~9.OUTPUTSELECT
rst => STATE~10.OUTPUTSELECT
rst => STATE~11.OUTPUTSELECT
rst => STATE~12.OUTPUTSELECT
rst => cmd_stop~0.OUTPUTSELECT
rst => cmd_start~0.OUTPUTSELECT
rst => cmd_send~2.OUTPUTSELECT
rst => execute~0.OUTPUTSELECT
rst => rom_addr~14.OUTPUTSELECT
rst => rom_addr~15.OUTPUTSELECT
rst => rom_addr~16.OUTPUTSELECT
rst => rom_addr~17.OUTPUTSELECT
rst => rom_addr~18.OUTPUTSELECT
rst => rom_addr~19.OUTPUTSELECT
rst => rom_addr~20.OUTPUTSELECT
rst => i2c_data_t~1.OUTPUTSELECT
rst => i2c_data_t~2.OUTPUTSELECT
rst => i2c_data_t~3.OUTPUTSELECT
rst => i2c_data_t~4.OUTPUTSELECT
rst => i2c_data_t~5.OUTPUTSELECT
rst => i2c_data_t~6.OUTPUTSELECT
rst => i2c_data_t~7.OUTPUTSELECT
rst => i2c_data_t~8.OUTPUTSELECT
rst => group_index~2.OUTPUTSELECT
rst => i2c_w_finish~1.OUTPUTSELECT
rst => STATE.IDLE.DATAIN
rom_data[0] => Select~16.IN1
rom_data[1] => Select~15.IN2
rom_data[2] => Select~14.IN1
rom_data[3] => Select~13.IN2
rom_data[4] => Select~12.IN1
rom_data[5] => Select~11.IN1
rom_data[6] => Select~10.IN1
rom_data[7] => Select~9.IN1
busy => Select~7.IN1
busy => Select~5.IN1
busy => Select~3.IN1
busy => Select~1.IN1
busy => STATE~0.OUTPUTSELECT
busy => STATE~2.DATAB
busy => STATE~1.OUTPUTSELECT
busy => rom_addr~7.OUTPUTSELECT
busy => rom_addr~8.OUTPUTSELECT
busy => rom_addr~9.OUTPUTSELECT
busy => rom_addr~10.OUTPUTSELECT
busy => rom_addr~11.OUTPUTSELECT
busy => rom_addr~12.OUTPUTSELECT
busy => rom_addr~13.OUTPUTSELECT
busy => Select~2.IN3
busy => Select~4.IN4
busy => Select~4.IN5
busy => Select~6.IN3
busy => Select~8.IN5
rom_addr[0] <= rom_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[1] <= rom_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[2] <= rom_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[3] <= rom_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[4] <= rom_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[5] <= rom_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[6] <= rom_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[0] <= i2c_data_t[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[1] <= i2c_data_t[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[2] <= i2c_data_t[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[3] <= i2c_data_t[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[4] <= i2c_data_t[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[5] <= i2c_data_t[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[6] <= i2c_data_t[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[7] <= i2c_data_t[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_stop <= cmd_stop~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_start <= cmd_start~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_send <= cmd_send~reg0.DB_MAX_OUTPUT_PORT_TYPE
execute <= execute~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_w_finish <= i2c_w_finish~reg0.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|SAA_ROM:inst2
address[0] => address[0]~6.IN1
address[1] => address[1]~5.IN1
address[2] => address[2]~4.IN1
address[3] => address[3]~3.IN1
address[4] => address[4]~2.IN1
address[5] => address[5]~1.IN1
address[6] => address[6]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|I2C_ALTERA|SAA_ROM:inst2|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_5qp:auto_generated.address_a[0]
address_a[1] => altsyncram_5qp:auto_generated.address_a[1]
address_a[2] => altsyncram_5qp:auto_generated.address_a[2]
address_a[3] => altsyncram_5qp:auto_generated.address_a[3]
address_a[4] => altsyncram_5qp:auto_generated.address_a[4]
address_a[5] => altsyncram_5qp:auto_generated.address_a[5]
address_a[6] => altsyncram_5qp:auto_generated.address_a[6]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_5qp:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_5qp:auto_generated.q_a[0]
q_a[1] <= altsyncram_5qp:auto_generated.q_a[1]
q_a[2] <= altsyncram_5qp:auto_generated.q_a[2]
q_a[3] <= altsyncram_5qp:auto_generated.q_a[3]
q_a[4] <= altsyncram_5qp:auto_generated.q_a[4]
q_a[5] <= altsyncram_5qp:auto_generated.q_a[5]
q_a[6] <= altsyncram_5qp:auto_generated.q_a[6]
q_a[7] <= altsyncram_5qp:auto_generated.q_a[7]
q_b[0] <= <GND>


|I2C_ALTERA|SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT


|I2C_ALTERA|I2C:inst10
sysclk => div_by_n:div_by_x.sysclk
sysclk => SDA_reg.CLK
sysclk => SCL_reg.CLK
sysclk => Cmd_reg[3].CLK
sysclk => Cmd_reg[2].CLK
sysclk => Cmd_reg[1].CLK
sysclk => Cmd_reg[0].CLK
sysclk => Start_condition.CLK
sysclk => Sh_reg[7].CLK
sysclk => Sh_reg[6].CLK
sysclk => Sh_reg[5].CLK
sysclk => Sh_reg[4].CLK
sysclk => Sh_reg[3].CLK
sysclk => Sh_reg[2].CLK
sysclk => Sh_reg[1].CLK
sysclk => Sh_reg[0].CLK
sysclk => BitCnt[2].CLK
sysclk => BitCnt[1].CLK
sysclk => BitCnt[0].CLK
sysclk => Ack_rx_reg.CLK
sysclk => Valid_data.CLK
sysclk => Ack_tx_reg.CLK
sysclk => Enable_reg.CLK
sysclk => Sx~1.IN1
sysclk => Ss~1.IN1
sysclk => Sy~1.IN1
sysclk => St~1.IN1
clk_en => div_by_n:div_by_x.cnt_en
/reset => SDA_reg.ACLR
/reset => SCL_reg.ACLR
/reset => Cmd_reg[3].ACLR
/reset => Cmd_reg[2].ACLR
/reset => Cmd_reg[1].ACLR
/reset => Cmd_reg[0].ACLR
/reset => Start_condition.ACLR
/reset => Sh_reg[7].ACLR
/reset => Sh_reg[6].ACLR
/reset => Sh_reg[5].ACLR
/reset => Sh_reg[4].ACLR
/reset => Sh_reg[3].ACLR
/reset => Sh_reg[2].ACLR
/reset => Sh_reg[1].ACLR
/reset => Sh_reg[0].ACLR
/reset => BitCnt[2].ACLR
/reset => BitCnt[1].ACLR
/reset => BitCnt[0].ACLR
/reset => Ack_rx_reg.ACLR
/reset => Valid_data.ACLR
/reset => Ack_tx_reg.ACLR
/reset => Enable_reg.ACLR
Dout[0] <= Sh_reg[0].DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Sh_reg[1].DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Sh_reg[2].DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Sh_reg[3].DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Sh_reg[4].DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Sh_reg[5].DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Sh_reg[6].DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Sh_reg[7].DB_MAX_OUTPUT_PORT_TYPE
Ack_rx <= Ack_rx_reg.DB_MAX_OUTPUT_PORT_TYPE
Status <= Start_condition.DB_MAX_OUTPUT_PORT_TYPE
DValid <= Valid_data.DB_MAX_OUTPUT_PORT_TYPE
DEnable <= Enable_reg.DB_MAX_OUTPUT_PORT_TYPE
SDA <= $00006
SCL <= $00007


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x
SysClk => lpm_counter:counter.clock
SysClk => Deglitch.CLK
cnt_en => lpm_counter:counter.cnt_en
Every_N <= Deglitch.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= lpm_counter:counter.q[0]
q[1] <= lpm_counter:counter.q[1]
q[2] <= lpm_counter:counter.q[2]
q[3] <= lpm_counter:counter.q[3]
q[4] <= lpm_counter:counter.q[4]


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_counter:counter
clock => cntr_986:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => cntr_986:auto_generated.cnt_en
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => cntr_986:auto_generated.sclr
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_986:auto_generated.q[0]
q[1] <= cntr_986:auto_generated.q[1]
q[2] <= cntr_986:auto_generated.q[2]
q[3] <= cntr_986:auto_generated.q[3]
q[4] <= cntr_986:auto_generated.q[4]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB
cout <= counter_cella4.COUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
sclr => counter_cella0.SCLR
sclr => counter_cella1.SCLR
sclr => counter_cella2.SCLR
sclr => counter_cella3.SCLR
sclr => counter_cella4.SCLR


|I2C_ALTERA|I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002
dataa[0] => comptree:comparator.dataa[0]
dataa[1] => comptree:comparator.dataa[1]
dataa[2] => comptree:comparator.dataa[2]
dataa[3] => comptree:comparator.dataa[3]
dataa[4] => comptree:comparator.dataa[4]
datab[0] => comptree:comparator.datab[0]
datab[1] => comptree:comparator.datab[1]
datab[2] => comptree:comparator.datab[2]
datab[3] => comptree:comparator.datab[3]
datab[4] => comptree:comparator.datab[4]
clock => ~NO_FANOUT~