📄 mux_1bb.tdf
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=4 LPM_WIDTH=7 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 4.2 cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ VERSION_END
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
--synthesis_resources = lut 14
SUBDESIGN mux_1bb
(
data[27..0] : input;
result[6..0] : output;
sel[1..0] : input;
)
VARIABLE
result_node[6..0] : WIRE;
sel_node[1..0] : WIRE;
w_data244w[3..0] : WIRE;
w_data274w[3..0] : WIRE;
w_data299w[3..0] : WIRE;
w_data324w[3..0] : WIRE;
w_data349w[3..0] : WIRE;
w_data374w[3..0] : WIRE;
w_data399w[3..0] : WIRE;
w_result245w : WIRE;
w_result255w : WIRE;
w_result256w : WIRE;
w_result275w : WIRE;
w_result285w : WIRE;
w_result286w : WIRE;
w_result300w : WIRE;
w_result310w : WIRE;
w_result311w : WIRE;
w_result325w : WIRE;
w_result335w : WIRE;
w_result336w : WIRE;
w_result350w : WIRE;
w_result360w : WIRE;
w_result361w : WIRE;
w_result375w : WIRE;
w_result385w : WIRE;
w_result386w : WIRE;
w_result400w : WIRE;
w_result410w : WIRE;
w_result411w : WIRE;
BEGIN
result[] = result_node[];
result_node[] = ( w_result400w, w_result375w, w_result350w, w_result325w, w_result300w, w_result275w, w_result245w);
sel_node[] = ( sel[1..0]);
w_data244w[] = ( data[21..21], data[14..14], data[7..7], data[0..0]);
w_data274w[] = ( data[22..22], data[15..15], data[8..8], data[1..1]);
w_data299w[] = ( data[23..23], data[16..16], data[9..9], data[2..2]);
w_data324w[] = ( data[24..24], data[17..17], data[10..10], data[3..3]);
w_data349w[] = ( data[25..25], data[18..18], data[11..11], data[4..4]);
w_data374w[] = ( data[26..26], data[19..19], data[12..12], data[5..5]);
w_data399w[] = ( data[27..27], data[20..20], data[13..13], data[6..6]);
w_result245w = w_result255w;
w_result255w = (((w_data244w[1..1] & sel_node[0..0]) & (! w_result256w)) # (w_result256w & (w_data244w[3..3] # (! sel_node[0..0]))));
w_result256w = (((w_data244w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data244w[2..2])));
w_result275w = w_result285w;
w_result285w = (((w_data274w[1..1] & sel_node[0..0]) & (! w_result286w)) # (w_result286w & (w_data274w[3..3] # (! sel_node[0..0]))));
w_result286w = (((w_data274w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data274w[2..2])));
w_result300w = w_result310w;
w_result310w = (((w_data299w[1..1] & sel_node[0..0]) & (! w_result311w)) # (w_result311w & (w_data299w[3..3] # (! sel_node[0..0]))));
w_result311w = (((w_data299w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data299w[2..2])));
w_result325w = w_result335w;
w_result335w = (((w_data324w[1..1] & sel_node[0..0]) & (! w_result336w)) # (w_result336w & (w_data324w[3..3] # (! sel_node[0..0]))));
w_result336w = (((w_data324w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data324w[2..2])));
w_result350w = w_result360w;
w_result360w = (((w_data349w[1..1] & sel_node[0..0]) & (! w_result361w)) # (w_result361w & (w_data349w[3..3] # (! sel_node[0..0]))));
w_result361w = (((w_data349w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data349w[2..2])));
w_result375w = w_result385w;
w_result385w = (((w_data374w[1..1] & sel_node[0..0]) & (! w_result386w)) # (w_result386w & (w_data374w[3..3] # (! sel_node[0..0]))));
w_result386w = (((w_data374w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data374w[2..2])));
w_result400w = w_result410w;
w_result410w = (((w_data399w[1..1] & sel_node[0..0]) & (! w_result411w)) # (w_result411w & (w_data399w[3..3] # (! sel_node[0..0]))));
w_result411w = (((w_data399w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data399w[2..2])));
END;
--VALID FILE
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