i2c_altera_hier_info

filter,很不错,大家可以看以下

|I2C_ALTERA
SCL <= I2C:inst1.SCL
SYSCLK => I2C:inst1.sysclk
SYSCLK => clk_div:inst3.clk_i
SYSCLK => SAA_ROM:inst2.clock
RST => I2C:inst1./reset
RST => i2c_cmd:inst.rst
SDA <= I2C:inst1.SDA


|I2C_ALTERA|I2C:inst1
sysclk => div_by_n:div_by_x.sysclk
sysclk => SDA_reg.CLK
sysclk => SCL_reg.CLK
sysclk => Cmd_reg[3].CLK
sysclk => Cmd_reg[2].CLK
sysclk => Cmd_reg[1].CLK
sysclk => Cmd_reg[0].CLK
sysclk => Start_condition.CLK
sysclk => Sh_reg[7].CLK
sysclk => Sh_reg[6].CLK
sysclk => Sh_reg[5].CLK
sysclk => Sh_reg[4].CLK
sysclk => Sh_reg[3].CLK
sysclk => Sh_reg[2].CLK
sysclk => Sh_reg[1].CLK
sysclk => Sh_reg[0].CLK
sysclk => BitCnt[2].CLK
sysclk => BitCnt[1].CLK
sysclk => BitCnt[0].CLK
sysclk => Ack_rx_reg.CLK
sysclk => Valid_data.CLK
sysclk => Ack_tx_reg.CLK
sysclk => Enable_reg.CLK
sysclk => Sx~1.IN1
sysclk => Ss~1.IN1
sysclk => Sy~1.IN1
sysclk => St~1.IN1
clk_en => div_by_n:div_by_x.cnt_en
/reset => SDA_reg.ACLR
/reset => SCL_reg.ACLR
/reset => Cmd_reg[3].ACLR
/reset => Cmd_reg[2].ACLR
/reset => Cmd_reg[1].ACLR
/reset => Cmd_reg[0].ACLR
/reset => Start_condition.ACLR
/reset => Sh_reg[7].ACLR
/reset => Sh_reg[6].ACLR
/reset => Sh_reg[5].ACLR
/reset => Sh_reg[4].ACLR
/reset => Sh_reg[3].ACLR
/reset => Sh_reg[2].ACLR
/reset => Sh_reg[1].ACLR
/reset => Sh_reg[0].ACLR
/reset => BitCnt[2].ACLR
/reset => BitCnt[1].ACLR
/reset => BitCnt[0].ACLR
/reset => Ack_rx_reg.ACLR
/reset => Valid_data.ACLR
/reset => Ack_tx_reg.ACLR
/reset => Enable_reg.ACLR
Dout[0] <= Sh_reg[0].DB_MAX_OUTPUT_PORT_TYPE
Dout[1] <= Sh_reg[1].DB_MAX_OUTPUT_PORT_TYPE
Dout[2] <= Sh_reg[2].DB_MAX_OUTPUT_PORT_TYPE
Dout[3] <= Sh_reg[3].DB_MAX_OUTPUT_PORT_TYPE
Dout[4] <= Sh_reg[4].DB_MAX_OUTPUT_PORT_TYPE
Dout[5] <= Sh_reg[5].DB_MAX_OUTPUT_PORT_TYPE
Dout[6] <= Sh_reg[6].DB_MAX_OUTPUT_PORT_TYPE
Dout[7] <= Sh_reg[7].DB_MAX_OUTPUT_PORT_TYPE
Ack_rx <= Ack_rx_reg.DB_MAX_OUTPUT_PORT_TYPE
Status <= Start_condition.DB_MAX_OUTPUT_PORT_TYPE
DValid <= Valid_data.DB_MAX_OUTPUT_PORT_TYPE
DEnable <= Enable_reg.DB_MAX_OUTPUT_PORT_TYPE
SDA <= $00006
SCL <= $00007


|I2C_ALTERA|I2C:inst1|div_by_n:div_by_x
SysClk => lpm_counter:counter.clock
SysClk => Deglitch.CLK
cnt_en => lpm_counter:counter.cnt_en
Every_N <= Deglitch.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= lpm_counter:counter.q[0]
q[1] <= lpm_counter:counter.q[1]


|I2C_ALTERA|I2C:inst1|div_by_n:div_by_x|lpm_counter:counter
clock => alt_counter_stratix:wysi_counter.clock
cnt_en => alt_counter_stratix:wysi_counter.cnt_en
sclr => alt_counter_stratix:wysi_counter.sclr
q[0] <= alt_counter_stratix:wysi_counter.q[0]
q[1] <= alt_counter_stratix:wysi_counter.q[1]
cout <= alt_counter_stratix:wysi_counter.cout


|I2C_ALTERA|I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|alt_counter_stratix:wysi_counter
clock => counter_cell[1].CLK
clock => counter_cell[0].CLK
clk_en => counter_cell[1].ENA
clk_en => counter_cell[0].ENA
cnt_en => counter_cell[1].DATAB
cnt_en => counter_cell[0].DATAB
sclr => counter_cell[1].SCLR
sclr => counter_cell[0].SCLR
aclr => counter_cell[1].ACLR
aclr => counter_cell[0].ACLR
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
cout <= cout_bit.COMBOUT


|I2C_ALTERA|I2C:inst1|div_by_n:div_by_x|lpm_compare:$00002
dataa[0] => comptree:comparator.dataa[0]
dataa[1] => comptree:comparator.dataa[1]
datab[0] => comptree:comparator.datab[0]
datab[1] => comptree:comparator.datab[1]
aeb <= aeb_xnode.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_xnode.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|I2C:inst1|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator
dataa[0] => cmpchain:cmp_end.dataa[0]
dataa[1] => cmpchain:cmp_end.dataa[1]
datab[0] => cmpchain:cmp_end.datab[0]
datab[1] => cmpchain:cmp_end.datab[1]
aeb <= cmpchain:cmp_end.aeb
agb <= <UNC>


|I2C_ALTERA|I2C:inst1|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator|cmpchain:cmp_end
aeb <= aeb_out.DB_MAX_OUTPUT_PORT_TYPE
agb <= agb_out.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|I2C:inst1|div_by_n:div_by_x|lpm_compare:$00002|altshift:aeb_ext_lat_ffs
data[0] => result[0].DATAIN
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|I2C:inst1|div_by_n:div_by_x|lpm_compare:$00002|altshift:agb_ext_lat_ffs
data[0] => result[0].DATAIN
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|i2c_cmd:inst
clk => cmd_stop~reg0.CLK
clk => cmd_start~reg0.CLK
clk => cmd_send~reg0.CLK
clk => execute~reg0.CLK
clk => rom_addr[6]~reg0.CLK
clk => rom_addr[5]~reg0.CLK
clk => rom_addr[4]~reg0.CLK
clk => rom_addr[3]~reg0.CLK
clk => rom_addr[2]~reg0.CLK
clk => rom_addr[1]~reg0.CLK
clk => rom_addr[0]~reg0.CLK
clk => i2c_data_t[7]~reg0.CLK
clk => i2c_data_t[6]~reg0.CLK
clk => i2c_data_t[5]~reg0.CLK
clk => i2c_data_t[4]~reg0.CLK
clk => i2c_data_t[3]~reg0.CLK
clk => i2c_data_t[2]~reg0.CLK
clk => i2c_data_t[1]~reg0.CLK
clk => i2c_data_t[0]~reg0.CLK
clk => group_index.CLK
clk => i2c_w_finish~reg0.CLK
clk => STATE~0.IN1
rst => i208.OUTPUTSELECT
rst => i209.OUTPUTSELECT
rst => i210.OUTPUTSELECT
rst => i211.OUTPUTSELECT
rst => i212.OUTPUTSELECT
rst => i213.OUTPUTSELECT
rst => i214.OUTPUTSELECT
rst => i215.OUTPUTSELECT
rst => i216.OUTPUTSELECT
rst => i217.OUTPUTSELECT
rst => i218.OUTPUTSELECT
rst => i219.OUTPUTSELECT
rst => i220.OUTPUTSELECT
rst => i221.OUTPUTSELECT
rst => i222.OUTPUTSELECT
rst => i223.OUTPUTSELECT
rst => i224.OUTPUTSELECT
rst => i225.OUTPUTSELECT
rst => i226.OUTPUTSELECT
rst => i227.OUTPUTSELECT
rst => i228.OUTPUTSELECT
rst => i229.OUTPUTSELECT
rst => i230.OUTPUTSELECT
rst => i231.OUTPUTSELECT
rst => i232.OUTPUTSELECT
rst => i233.OUTPUTSELECT
rst => i234.OUTPUTSELECT
rst => i235.OUTPUTSELECT
rst => i236.OUTPUTSELECT
rst => i237.OUTPUTSELECT
rst => i238.OUTPUTSELECT
rst => i239.OUTPUTSELECT
rom_data[0] => i~22.IN1
rom_data[1] => i~21.IN2
rom_data[2] => i~20.IN1
rom_data[3] => i~19.IN2
rom_data[4] => i~18.IN1
rom_data[5] => i~17.IN1
rom_data[6] => i~16.IN1
rom_data[7] => i~15.IN1
busy => i5.OUTPUTSELECT
busy => i6.OUTPUTSELECT
busy => i7.OUTPUTSELECT
busy => i8.OUTPUTSELECT
busy => i9.OUTPUTSELECT
busy => i10.OUTPUTSELECT
busy => i11.OUTPUTSELECT
busy => i12.OUTPUTSELECT
busy => i13.OUTPUTSELECT
busy => i14.OUTPUTSELECT
busy => i15.OUTPUTSELECT
busy => i36.OUTPUTSELECT
busy => i38.OUTPUTSELECT
busy => i59.OUTPUTSELECT
busy => i103.OUTPUTSELECT
busy => i86.OUTPUTSELECT
busy => i88.OUTPUTSELECT
busy => i94.OUTPUTSELECT
busy => i95.OUTPUTSELECT
busy => i96.OUTPUTSELECT
busy => i97.OUTPUTSELECT
busy => i98.OUTPUTSELECT
busy => i99.OUTPUTSELECT
busy => i100.OUTPUTSELECT
busy => i17.OUTPUTSELECT
busy => i18.OUTPUTSELECT
busy => i19.OUTPUTSELECT
busy => i20.OUTPUTSELECT
busy => i21.OUTPUTSELECT
busy => i22.OUTPUTSELECT
busy => i23.OUTPUTSELECT
busy => i24.OUTPUTSELECT
busy => i25.OUTPUTSELECT
busy => i26.OUTPUTSELECT
busy => i27.OUTPUTSELECT
busy => i114.OUTPUTSELECT
busy => i49.OUTPUTSELECT
busy => i51.OUTPUTSELECT
rom_addr[0] <= rom_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[1] <= rom_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[2] <= rom_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[3] <= rom_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[4] <= rom_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[5] <= rom_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rom_addr[6] <= rom_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[0] <= i2c_data_t[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[1] <= i2c_data_t[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[2] <= i2c_data_t[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[3] <= i2c_data_t[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[4] <= i2c_data_t[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[5] <= i2c_data_t[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[6] <= i2c_data_t[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_data_t[7] <= i2c_data_t[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_stop <= cmd_stop~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_start <= cmd_start~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_send <= cmd_send~reg0.DB_MAX_OUTPUT_PORT_TYPE
execute <= execute~reg0.DB_MAX_OUTPUT_PORT_TYPE
i2c_w_finish <= i2c_w_finish~reg0.DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|clk_div:inst3
clk_i => Cnt[0].CLK
clk_i => Cnt[1].CLK
clk_4 <= Cnt[1].DB_MAX_OUTPUT_PORT_TYPE


|I2C_ALTERA|SAA_ROM:inst2
address[0] => address[0]~6.IN1
address[1] => address[1]~5.IN1
address[2] => address[2]~4.IN1
address[3] => address[3]~3.IN1
address[4] => address[4]~2.IN1
address[5] => address[5]~1.IN1
address[6] => address[6]~0.IN1
clock => clock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|I2C_ALTERA|SAA_ROM:inst2|altsyncram:altsyncram_component
address_a[0] => altsyncram_thj:auto_generated.address_a[0]
address_a[1] => altsyncram_thj:auto_generated.address_a[1]
address_a[2] => altsyncram_thj:auto_generated.address_a[2]
address_a[3] => altsyncram_thj:auto_generated.address_a[3]
address_a[4] => altsyncram_thj:auto_generated.address_a[4]
address_a[5] => altsyncram_thj:auto_generated.address_a[5]
address_a[6] => altsyncram_thj:auto_generated.address_a[6]
clock0 => altsyncram_thj:auto_generated.clock0
q_a[0] <= altsyncram_thj:auto_generated.q_a[0]
q_a[1] <= altsyncram_thj:auto_generated.q_a[1]
q_a[2] <= altsyncram_thj:auto_generated.q_a[2]
q_a[3] <= altsyncram_thj:auto_generated.q_a[3]
q_a[4] <= altsyncram_thj:auto_generated.q_a[4]
q_a[5] <= altsyncram_thj:auto_generated.q_a[5]
q_a[6] <= altsyncram_thj:auto_generated.q_a[6]
q_a[7] <= altsyncram_thj:auto_generated.q_a[7]
q_b[0] <= <UNC>


|I2C_ALTERA|SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_thj:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT