📄 altsyncram_nl82.tdf
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PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 5,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 28672,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 5,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a36 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 28672,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 5,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 28672,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 5,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a37 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 28672,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 5,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 28672,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 5,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a38 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 28672,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 5,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 28672,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 5,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a39 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 28672,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 5,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 28672,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 5,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
address_a_wire[14..0] : WIRE;
address_b_wire[14..0] : WIRE;
clocken1 : NODE;
BEGIN
address_reg_b[].CLK = clock1;
address_reg_b[].D = address_b[14..12];
address_reg_b[].ENA = clocken1;
decode2.data[2..0] = address_a_wire[14..12];
decode2.enable = wren_a;
mux3.data[] = ( ram_block1a[39].portbdataout[0..0], ram_block1a[38].portbdataout[0..0], ram_block1a[37].portbdataout[0..0], ram_block1a[36].portbdataout[0..0], ram_block1a[35].portbdataout[0..0], ram_block1a[34].portbdataout[0..0], ram_block1a[33].portbdataout[0..0], ram_block1a[32].portbdataout[0..0], ram_block1a[31].portbdataout[0..0], ram_block1a[30].portbdataout[0..0], ram_block1a[29].portbdataout[0..0], ram_block1a[28].portbdataout[0..0], ram_block1a[27].portbdataout[0..0], ram_block1a[26].portbdataout[0..0], ram_block1a[25].portbdataout[0..0], ram_block1a[24].portbdataout[0..0], ram_block1a[23].portbdataout[0..0], ram_block1a[22].portbdataout[0..0], ram_block1a[21].portbdataout[0..0], ram_block1a[20].portbdataout[0..0], ram_block1a[19].portbdataout[0..0], ram_block1a[18].portbdataout[0..0], ram_block1a[17].portbdataout[0..0], ram_block1a[16].portbdataout[0..0], ram_block1a[15].portbdataout[0..0], ram_block1a[14].portbdataout[0..0], ram_block1a[13].portbdataout[0..0], ram_block1a[12].portbdataout[0..0], ram_block1a[11].portbdataout[0..0], ram_block1a[10].portbdataout[0..0], ram_block1a[9].portbdataout[0..0], ram_block1a[8].portbdataout[0..0], ram_block1a[7].portbdataout[0..0], ram_block1a[6].portbdataout[0..0], ram_block1a[5].portbdataout[0..0], ram_block1a[4].portbdataout[0..0], ram_block1a[3].portbdataout[0..0], ram_block1a[2].portbdataout[0..0], ram_block1a[1].portbdataout[0..0], ram_block1a[0].portbdataout[0..0]);
mux3.sel[] = address_reg_b[].Q;
ram_block1a[39..0].clk0 = clock0;
ram_block1a[39..0].clk1 = clock1;
ram_block1a[0].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[1].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[2].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[3].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[4].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[5].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[6].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[7].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[8].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[9].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[10].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[11].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[12].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[13].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[14].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[15].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[16].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[17].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[18].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[19].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[20].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[21].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[22].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[23].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[24].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[25].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[26].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[27].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[28].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[29].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[30].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[31].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[32].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[33].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[34].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[35].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[36].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[37].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[38].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[39].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[0..0]);
ram_block1a[6].portadatain[] = ( data_a[1..1]);
ram_block1a[7].portadatain[] = ( data_a[2..2]);
ram_block1a[8].portadatain[] = ( data_a[3..3]);
ram_block1a[9].portadatain[] = ( data_a[4..4]);
ram_block1a[10].portadatain[] = ( data_a[0..0]);
ram_block1a[11].portadatain[] = ( data_a[1..1]);
ram_block1a[12].portadatain[] = ( data_a[2..2]);
ram_block1a[13].portadatain[] = ( data_a[3..3]);
ram_block1a[14].portadatain[] = ( data_a[4..4]);
ram_block1a[15].portadatain[] = ( data_a[0..0]);
ram_block1a[16].portadatain[] = ( data_a[1..1]);
ram_block1a[17].portadatain[] = ( data_a[2..2]);
ram_block1a[18].portadatain[] = ( data_a[3..3]);
ram_block1a[19].portadatain[] = ( data_a[4..4]);
ram_block1a[20].portadatain[] = ( data_a[0..0]);
ram_block1a[21].portadatain[] = ( data_a[1..1]);
ram_block1a[22].portadatain[] = ( data_a[2..2]);
ram_block1a[23].portadatain[] = ( data_a[3..3]);
ram_block1a[24].portadatain[] = ( data_a[4..4]);
ram_block1a[25].portadatain[] = ( data_a[0..0]);
ram_block1a[26].portadatain[] = ( data_a[1..1]);
ram_block1a[27].portadatain[] = ( data_a[2..2]);
ram_block1a[28].portadatain[] = ( data_a[3..3]);
ram_block1a[29].portadatain[] = ( data_a[4..4]);
ram_block1a[30].portadatain[] = ( data_a[0..0]);
ram_block1a[31].portadatain[] = ( data_a[1..1]);
ram_block1a[32].portadatain[] = ( data_a[2..2]);
ram_block1a[33].portadatain[] = ( data_a[3..3]);
ram_block1a[34].portadatain[] = ( data_a[4..4]);
ram_block1a[35].portadatain[] = ( data_a[0..0]);
ram_block1a[36].portadatain[] = ( data_a[1..1]);
ram_block1a[37].portadatain[] = ( data_a[2..2]);
ram_block1a[38].portadatain[] = ( data_a[3..3]);
ram_block1a[39].portadatain[] = ( data_a[4..4]);
ram_block1a[0].portawe = decode2.eq[0..0];
ram_block1a[1].portawe = decode2.eq[0..0];
ram_block1a[2].portawe = decode2.eq[0..0];
ram_block1a[3].portawe = decode2.eq[0..0];
ram_block1a[4].portawe = decode2.eq[0..0];
ram_block1a[5].portawe = decode2.eq[1..1];
ram_block1a[6].portawe = decode2.eq[1..1];
ram_block1a[7].portawe = decode2.eq[1..1];
ram_block1a[8].portawe = decode2.eq[1..1];
ram_block1a[9].portawe = decode2.eq[1..1];
ram_block1a[10].portawe = decode2.eq[2..2];
ram_block1a[11].portawe = decode2.eq[2..2];
ram_block1a[12].portawe = decode2.eq[2..2];
ram_block1a[13].portawe = decode2.eq[2..2];
ram_block1a[14].portawe = decode2.eq[2..2];
ram_block1a[15].portawe = decode2.eq[3..3];
ram_block1a[16].portawe = decode2.eq[3..3];
ram_block1a[17].portawe = decode2.eq[3..3];
ram_block1a[18].portawe = decode2.eq[3..3];
ram_block1a[19].portawe = decode2.eq[3..3];
ram_block1a[20].portawe = decode2.eq[4..4];
ram_block1a[21].portawe = decode2.eq[4..4];
ram_block1a[22].portawe = decode2.eq[4..4];
ram_block1a[23].portawe = decode2.eq[4..4];
ram_block1a[24].portawe = decode2.eq[4..4];
ram_block1a[25].portawe = decode2.eq[5..5];
ram_block1a[26].portawe = decode2.eq[5..5];
ram_block1a[27].portawe = decode2.eq[5..5];
ram_block1a[28].portawe = decode2.eq[5..5];
ram_block1a[29].portawe = decode2.eq[5..5];
ram_block1a[30].portawe = decode2.eq[6..6];
ram_block1a[31].portawe = decode2.eq[6..6];
ram_block1a[32].portawe = decode2.eq[6..6];
ram_block1a[33].portawe = decode2.eq[6..6];
ram_block1a[34].portawe = decode2.eq[6..6];
ram_block1a[35].portawe = decode2.eq[7..7];
ram_block1a[36].portawe = decode2.eq[7..7];
ram_block1a[37].portawe = decode2.eq[7..7];
ram_block1a[38].portawe = decode2.eq[7..7];
ram_block1a[39].portawe = decode2.eq[7..7];
ram_block1a[0].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[1].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[2].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[3].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[4].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[5].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[6].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[7].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[8].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[9].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[10].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[11].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[12].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[13].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[14].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[15].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[16].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[17].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[18].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[19].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[20].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[21].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[22].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[23].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[24].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[25].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[26].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[27].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[28].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[29].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[30].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[31].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[32].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[33].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[34].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[35].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[36].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[37].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[38].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[39].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[0].portbrewe = B"1";
ram_block1a[1].portbrewe = B"1";
ram_block1a[2].portbrewe = B"1";
ram_block1a[3].portbrewe = B"1";
ram_block1a[4].portbrewe = B"1";
ram_block1a[5].portbrewe = B"1";
ram_block1a[6].portbrewe = B"1";
ram_block1a[7].portbrewe = B"1";
ram_block1a[8].portbrewe = B"1";
ram_block1a[9].portbrewe = B"1";
ram_block1a[10].portbrewe = B"1";
ram_block1a[11].portbrewe = B"1";
ram_block1a[12].portbrewe = B"1";
ram_block1a[13].portbrewe = B"1";
ram_block1a[14].portbrewe = B"1";
ram_block1a[15].portbrewe = B"1";
ram_block1a[16].portbrewe = B"1";
ram_block1a[17].portbrewe = B"1";
ram_block1a[18].portbrewe = B"1";
ram_block1a[19].portbrewe = B"1";
ram_block1a[20].portbrewe = B"1";
ram_block1a[21].portbrewe = B"1";
ram_block1a[22].portbrewe = B"1";
ram_block1a[23].portbrewe = B"1";
ram_block1a[24].portbrewe = B"1";
ram_block1a[25].portbrewe = B"1";
ram_block1a[26].portbrewe = B"1";
ram_block1a[27].portbrewe = B"1";
ram_block1a[28].portbrewe = B"1";
ram_block1a[29].portbrewe = B"1";
ram_block1a[30].portbrewe = B"1";
ram_block1a[31].portbrewe = B"1";
ram_block1a[32].portbrewe = B"1";
ram_block1a[33].portbrewe = B"1";
ram_block1a[34].portbrewe = B"1";
ram_block1a[35].portbrewe = B"1";
ram_block1a[36].portbrewe = B"1";
ram_block1a[37].portbrewe = B"1";
ram_block1a[38].portbrewe = B"1";
ram_block1a[39].portbrewe = B"1";
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
clocken1 = VCC;
q_b[] = mux3.result[];
END;
--VALID FILE
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