i2c_altera.map.qmsg

来自「filter,很不错,大家可以看以下」· QMSG 代码 · 共 206 行 · 第 1/5 页

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_slr.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_slr.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_slr " "Info: Found entity 1: altsyncram_slr" {  } { { "db/altsyncram_slr.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_slr.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_slr ENC_ROM:inst16\|altsyncram:altsyncram_component\|altsyncram_slr:auto_generated " "Info: Elaborating entity \"altsyncram_slr\" for hierarchy \"ENC_ROM:inst16\|altsyncram:altsyncram_component\|altsyncram_slr:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_mask add_mask:inst22 " "Info: Elaborating entity \"add_mask\" for hierarchy \"add_mask:inst22\"" {  } { { "I2C_ALTERA.bdf" "inst22" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1208 2144 2304 1336 "inst22" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mask_rom add_mask:inst22\|mask_rom:mask_rom0 " "Info: Elaborating entity \"mask_rom\" for hierarchy \"add_mask:inst22\|mask_rom:mask_rom0\"" {  } { { "add_mask.v" "mask_rom0" { Text "D:/VieoColorBar/Proj/add_mask.v" 125 -1 0 } }  } 0}
{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "q_b altsyncram_component mask_rom.v(54) " "Info: (10265) Verilog HDL Module Instantiation information at mask_rom.v(54): instance \"altsyncram_component\" connects port \"q_b\" to an empty expression" {  } { { "mask_rom.v" "" { Text "D:/VieoColorBar/Proj/mask_rom.v" 54 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\"" {  } { { "mask_rom.v" "altsyncram_component" { Text "D:/VieoColorBar/Proj/mask_rom.v" 67 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_j1t.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_j1t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_j1t " "Info: Found entity 1: altsyncram_j1t" {  } { { "db/altsyncram_j1t.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_j1t.tdf" 38 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_j1t add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated " "Info: Elaborating entity \"altsyncram_j1t\" for hierarchy \"add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_iga.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_iga.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_iga " "Info: Found entity 1: decode_iga" {  } { { "db/decode_iga.tdf" "" { Text "D:/VieoColorBar/Proj/db/decode_iga.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_iga add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|decode_iga:deep_decode " "Info: Elaborating entity \"decode_iga\" for hierarchy \"add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|decode_iga:deep_decode\"" {  } { { "db/altsyncram_j1t.tdf" "deep_decode" { Text "D:/VieoColorBar/Proj/db/altsyncram_j1t.tdf" 46 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_rab.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_rab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_rab " "Info: Found entity 1: mux_rab" {  } { { "db/mux_rab.tdf" "" { Text "D:/VieoColorBar/Proj/db/mux_rab.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_rab add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|mux_rab:mux2 " "Info: Elaborating entity \"mux_rab\" for hierarchy \"add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|mux_rab:mux2\"" {  } { { "db/altsyncram_j1t.tdf" "mux2" { Text "D:/VieoColorBar/Proj/db/altsyncram_j1t.tdf" 47 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset_gen reset_gen:inst21 " "Info: Elaborating entity \"reset_gen\" for hierarchy \"reset_gen:inst21\"" {  } { { "I2C_ALTERA.bdf" "inst21" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1232 1520 1632 1328 "inst21" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "receiver receiver:inst18 " "Info: Elaborating entity \"receiver\" for hierarchy \"receiver:inst18\"" {  } { { "I2C_ALTERA.bdf" "inst18" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1224 1832 2016 1352 "inst18" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 receiver.v(70) " "Warning: Verilog HDL assignment warning at receiver.v(70): truncated value with size 32 to match size of target (3)" {  } { { "receiver.v" "" { Text "D:/VieoColorBar/Proj/receiver.v" 70 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Led_run Led_run:inst14 " "Info: Elaborating entity \"Led_run\" for hierarchy \"Led_run:inst14\"" {  } { { "I2C_ALTERA.bdf" "inst14" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 704 304 400 800 "inst14" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 Led_run.v(14) " "Warning: Verilog HDL assignment warning at Led_run.v(14): truncated value with size 32 to match size of target (24)" {  } { { "Led_run.v" "" { Text "D:/VieoColorBar/Proj/Led_run.v" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 Led_run.v(18) " "Warning: Verilog HDL assignment warning at Led_run.v(18): truncated value with size 32 to match size of target (24)" {  } { { "Led_run.v" "" { Text "D:/VieoColorBar/Proj/Led_run.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Led_run.v(31) " "Warning: Verilog HDL assignment warning at Led_run.v(31): truncated value with size 32 to match size of target (1)" {  } { { "Led_run.v" "" { Text "D:/VieoColorBar/Proj/Led_run.v" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Led_run.v(36) " "Warning: Verilog HDL assignment warning at Led_run.v(36): truncated value with size 32 to match size of target (1)" {  } { { "Led_run.v" "" { Text "D:/VieoColorBar/Proj/Led_run.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 Led_run.v(39) " "Warning: Verilog HDL assignment warning at Led_run.v(39): truncated value with size 32 to match size of target (1)" {  } { { "Led_run.v" "" { Text "D:/VieoColorBar/Proj/Led_run.v" 39 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "I2C:inst10\|Cmd_reg\[3\] data_in GND " "Warning: Reduced register \"I2C:inst10\|Cmd_reg\[3\]\" with stuck data_in port to stuck value GND" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 101 10 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "I2C:inst10\|Ack_tx_reg data_in GND " "Warning: Reduced register \"I2C:inst10\|Ack_tx_reg\" with stuck data_in port to stuck value GND" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 107 3 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "I2C:inst1\|Cmd_reg\[3\] data_in GND " "Warning: Reduced register \"I2C:inst1\|Cmd_reg\[3\]\" with stuck data_in port to stuck value GND" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 101 10 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "I2C:inst1\|Ack_tx_reg data_in GND " "Warning: Reduced register \"I2C:inst1\|Ack_tx_reg\" with stuck data_in port to stuck value GND" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 107 3 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|add_mask:inst22\|STATE 5 0 " "Info: State machine \"\|I2C_ALTERA\|add_mask:inst22\|STATE\" contains 5 states and 0 state bits" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 43 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|i2c_cmd_7128:inst17\|STATE 11 0 " "Info: State machine \"\|I2C_ALTERA\|i2c_cmd_7128:inst17\|STATE\" contains 11 states and 0 state bits" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 23 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|I2C:inst10\|Sx 2 0 " "Info: State machine \"\|I2C_ALTERA\|I2C:inst10\|Sx\" contains 2 states and 0 state bits" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 89 3 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|I2C:inst10\|Ss 7 0 " "Info: State machine \"\|I2C_ALTERA\|I2C:inst10\|Ss\" contains 7 states and 0 state bits" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 92 3 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|I2C:inst10\|Sy 4 0 " "Info: State machine \"\|I2C_ALTERA\|I2C:inst10\|Sy\" contains 4 states and 0 state bits" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 95 3 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|I2C:inst10\|St 9 0 " "Info: State machine \"\|I2C_ALTERA\|I2C:inst10\|St\" contains 9 states and 0 state bits" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 98 3 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|i2c_cmd:inst\|STATE 11 0 " "Info: State machine \"\|I2C_ALTERA\|i2c_cmd:inst\|STATE\" contains 11 states and 0 state bits" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 23 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|I2C:inst1\|Sx 2 0 " "Info: State machine \"\|I2C_ALTERA\|I2C:inst1\|Sx\" contains 2 states and 0 state bits" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 89 3 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|I2C:inst1\|Ss 7 0 " "Info: State machine \"\|I2C_ALTERA\|I2C:inst1\|Ss\" contains 7 states and 0 state bits" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 92 3 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|I2C:inst1\|Sy 4 0 " "Info: State machine \"\|I2C_ALTERA\|I2C:inst1\|Sy\" contains 4 states and 0 state bits" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 95 3 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|I2C_ALTERA\|I2C:inst1\|St 9 0 " "Info: State machine \"\|I2C_ALTERA\|I2C:inst1\|St\" contains 9 states and 0 state bits" {  } { { "I2C.TDF" "" { Text "D:/VieoColorBar/Proj/I2C.TDF" 98 3 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|I2C_ALTERA\|add_mask:inst22\|STATE " "Info: Selected Auto state machine encoding method for state machine \"\|I2C_ALTERA\|add_mask:inst22\|STATE\"" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 43 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|I2C_ALTERA\|add_mask:inst22\|STATE " "Info: Encoding result for state machine \"\|I2C_ALTERA\|add_mask:inst22\|STATE\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "add_mask:inst22\|STATE.001 " "Info: Encoded state bit \"add_mask:inst22\|STATE.001\"" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 43 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "add_mask:inst22\|STATE.010 " "Info: Encoded state bit \"add_mask:inst22\|STATE.010\"" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 43 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "add_mask:inst22\|STATE.011 " "Info: Encoded state bit \"add_mask:inst22\|STATE.011\"" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 43 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "add_mask:inst22\|STATE.000 " "Info: Encoded state bit \"add_mask:inst22\|STATE.000\"" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 43 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "add_mask:inst22\|STATE.100 " "Info: Encoded state bit \"add_mask:inst22\|STATE.100\"" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 43 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|I2C_ALTERA\|add_mask:inst22\|STATE.000 00000 " "Info: State \"\|I2C_ALTERA\|add_mask:inst22\|STATE.000\" uses code string \"00000\"" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 43 -1 0 } }  } 0} { "Info" "IOPT_SM