i2c_altera.map.qmsg

来自「filter,很不错,大家可以看以下」· QMSG 代码 · 共 206 行 · 第 1/5 页

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(134) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(134): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(140) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(140): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 140 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "SAA_ROM.v 1 1 " "Info: Using design file SAA_ROM.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SAA_ROM " "Info: Found entity 1: SAA_ROM" {  } { { "SAA_ROM.v" "" { Text "D:/VieoColorBar/Proj/SAA_ROM.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SAA_ROM SAA_ROM:inst2 " "Info: Elaborating entity \"SAA_ROM\" for hierarchy \"SAA_ROM:inst2\"" {  } { { "I2C_ALTERA.bdf" "inst2" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1208 1072 1232 1288 "inst2" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram SAA_ROM:inst2\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"SAA_ROM:inst2\|altsyncram:altsyncram_component\"" {  } { { "SAA_ROM.v" "altsyncram_component" { Text "D:/VieoColorBar/Proj/SAA_ROM.v" 71 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_5qp.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5qp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_5qp " "Info: Found entity 1: altsyncram_5qp" {  } { { "db/altsyncram_5qp.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_5qp.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_5qp SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated " "Info: Elaborating entity \"altsyncram_5qp\" for hierarchy \"SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_cmd_7128 i2c_cmd_7128:inst17 " "Info: Elaborating entity \"i2c_cmd_7128\" for hierarchy \"i2c_cmd_7128:inst17\"" {  } { { "I2C_ALTERA.bdf" "inst17" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 256 904 1104 416 "inst17" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(32) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(32): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(33) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(33): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(34) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(34): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(35) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(35): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 i2c_cmd_7128.v(36) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(36): truncated value with size 32 to match size of target (7)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c_cmd_7128.v(37) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(37): truncated value with size 32 to match size of target (8)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 37 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(38) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(38): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 38 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(39) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(39): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 39 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c_cmd_7128.v(47) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(47): truncated value with size 32 to match size of target (8)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 47 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(48) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(48): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(49) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(49): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(56) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(56): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 56 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(57) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(57): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 57 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c_cmd_7128.v(65) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(65): truncated value with size 32 to match size of target (8)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(66) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(66): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(67) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(67): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(75) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(75): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 75 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(76) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(76): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 76 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 i2c_cmd_7128.v(77) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(77): truncated value with size 32 to match size of target (7)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 77 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(85) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(85): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(86) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(86): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 86 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(94) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(94): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 94 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(95) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(95): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 95 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 i2c_cmd_7128.v(102) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(102): truncated value with size 32 to match size of target (7)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(110) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(110): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 110 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(111) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(111): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 111 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(118) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(118): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(119) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(119): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 119 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(134) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(134): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd_7128.v(140) " "Warning: Verilog HDL assignment warning at i2c_cmd_7128.v(140): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 140 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "ENC_ROM.v 1 1 " "Info: Using design file ENC_ROM.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ENC_ROM " "Info: Found entity 1: ENC_ROM" {  } { { "ENC_ROM.v" "" { Text "D:/VieoColorBar/Proj/ENC_ROM.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ENC_ROM ENC_ROM:inst16 " "Info: Elaborating entity \"ENC_ROM\" for hierarchy \"ENC_ROM:inst16\"" {  } { { "I2C_ALTERA.bdf" "inst16" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 544 1080 1296 680 "inst16" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ENC_ROM:inst16\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ENC_ROM:inst16\|altsyncram:altsyncram_component\"" {  } { { "ENC_ROM.v" "altsyncram_component" { Text "D:/VieoColorBar/Proj/ENC_ROM.v" 71 -1 0 } }  } 0}