i2c_altera.map.qmsg

来自「filter,很不错,大家可以看以下」· QMSG 代码 · 共 206 行 · 第 1/5 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen clk_gen:inst19 " "Info: Elaborating entity \"clk_gen\" for hierarchy \"clk_gen:inst19\"" {  } { { "I2C_ALTERA.bdf" "inst19" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1400 920 1016 1496 "inst19" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clk_gen.v(19) " "Warning: Verilog HDL assignment warning at clk_gen.v(19): truncated value with size 32 to match size of target (2)" {  } { { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clk_gen.v(20) " "Warning: Verilog HDL assignment warning at clk_gen.v(20): truncated value with size 32 to match size of target (1)" {  } { { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clk_gen.v(24) " "Warning: Verilog HDL assignment warning at clk_gen.v(24): truncated value with size 32 to match size of target (2)" {  } { { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 clk_gen.v(27) " "Warning: Verilog HDL assignment warning at clk_gen.v(27): truncated value with size 32 to match size of target (2)" {  } { { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 27 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "PLL.v 1 1 " "Info: Using design file PLL.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 PLL " "Info: Found entity 1: PLL" {  } { { "PLL.v" "" { Text "D:/VieoColorBar/Proj/PLL.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL PLL:inst26 " "Info: Elaborating entity \"PLL\" for hierarchy \"PLL:inst26\"" {  } { { "I2C_ALTERA.bdf" "inst26" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1368 536 792 1552 "inst26" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus50/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus50/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLL:inst26\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLL:inst26\|altpll:altpll_component\"" {  } { { "PLL.v" "altpll_component" { Text "D:/VieoColorBar/Proj/PLL.v" 92 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "filter filter:inst8 " "Info: Elaborating entity \"filter\" for hierarchy \"filter:inst8\"" {  } { { "I2C_ALTERA.bdf" "inst8" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 936 568 680 1032 "inst8" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 filter.v(11) " "Warning: Verilog HDL assignment warning at filter.v(11): truncated value with size 32 to match size of target (16)" {  } { { "filter.v" "" { Text "D:/VieoColorBar/Proj/filter.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 filter.v(19) " "Warning: Verilog HDL assignment warning at filter.v(19): truncated value with size 32 to match size of target (1)" {  } { { "filter.v" "" { Text "D:/VieoColorBar/Proj/filter.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 filter.v(21) " "Warning: Verilog HDL assignment warning at filter.v(21): truncated value with size 32 to match size of target (1)" {  } { { "filter.v" "" { Text "D:/VieoColorBar/Proj/filter.v" 21 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_cmd i2c_cmd:inst " "Info: Elaborating entity \"i2c_cmd\" for hierarchy \"i2c_cmd:inst\"" {  } { { "I2C_ALTERA.bdf" "inst" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 920 896 1096 1080 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(32) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(32): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(33) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(33): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(34) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(34): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(35) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(35): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 i2c_cmd.v(36) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(36): truncated value with size 32 to match size of target (7)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c_cmd.v(37) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(37): truncated value with size 32 to match size of target (8)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 37 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(38) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(38): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 38 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(39) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(39): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 39 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c_cmd.v(47) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(47): truncated value with size 32 to match size of target (8)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 47 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(48) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(48): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(49) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(49): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(56) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(56): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 56 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(57) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(57): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 57 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c_cmd.v(65) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(65): truncated value with size 32 to match size of target (8)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 65 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(66) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(66): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 66 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(67) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(67): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 67 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(75) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(75): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 75 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(76) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(76): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 76 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 i2c_cmd.v(77) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(77): truncated value with size 32 to match size of target (7)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 77 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(85) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(85): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 85 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(86) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(86): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 86 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(94) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(94): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 94 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(95) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(95): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 95 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 i2c_cmd.v(102) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(102): truncated value with size 32 to match size of target (7)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(110) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(110): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 110 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(111) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(111): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 111 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(118) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(118): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c_cmd.v(119) " "Warning: Verilog HDL assignment warning at i2c_cmd.v(119): truncated value with size 32 to match size of target (1)" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 119 0 0 } }  } 0}