i2c_altera.map.qmsg

来自「filter,很不错,大家可以看以下」· QMSG 代码 · 共 206 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 14 14:53:24 2006 " "Info: Processing started: Mon Aug 14 14:53:24 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RVDK_Sample -c I2C_ALTERA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RVDK_Sample -c I2C_ALTERA" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "source720_576_25Hz.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file source720_576_25Hz.v" { { "Info" "ISGN_ENTITY_NAME" "1 source720_576_25Hz " "Info: Found entity 1: source720_576_25Hz" {  } { { "source720_576_25Hz.v" "" { Text "D:/VieoColorBar/Proj/source720_576_25Hz.v" 40 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sync_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sync_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 sync_gen " "Info: Found entity 1: sync_gen" {  } { { "sync_gen.v" "" { Text "D:/VieoColorBar/Proj/sync_gen.v" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_out.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file vga_out.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_out " "Info: Found entity 1: vga_out" {  } { { "vga_out.v" "" { Text "D:/VieoColorBar/Proj/vga_out.v" 40 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Command.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Command.v" { { "Info" "ISGN_ENTITY_NAME" "1 command " "Info: Found entity 1: command" {  } { { "Command.v" "" { Text "D:/VieoColorBar/Proj/Command.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control_interface.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file control_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_interface " "Info: Found entity 1: control_interface" {  } { { "control_interface.v" "" { Text "D:/VieoColorBar/Proj/control_interface.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "datacnl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file datacnl.v" { { "Info" "ISGN_ENTITY_NAME" "1 datacnl " "Info: Found entity 1: datacnl" {  } { { "datacnl.v" "" { Text "D:/VieoColorBar/Proj/datacnl.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "clk mesure_card_top.v(59) " "Warning: Verilog HDL net warning at mesure_card_top.v(59): created undeclared net \"clk\"" {  } { { "mesure_card_top.v" "" { Text "D:/VieoColorBar/Proj/mesure_card_top.v" 59 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "start_read mesure_card_top.v(96) " "Warning: Verilog HDL net warning at mesure_card_top.v(96): created undeclared net \"start_read\"" {  } { { "mesure_card_top.v" "" { Text "D:/VieoColorBar/Proj/mesure_card_top.v" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "s_ram_wen mesure_card_top.v(132) " "Warning: Verilog HDL net warning at mesure_card_top.v(132): created undeclared net \"s_ram_wen\"" {  } { { "mesure_card_top.v" "" { Text "D:/VieoColorBar/Proj/mesure_card_top.v" 132 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "s_req mesure_card_top.v(133) " "Warning: Verilog HDL net warning at mesure_card_top.v(133): created undeclared net \"s_req\"" {  } { { "mesure_card_top.v" "" { Text "D:/VieoColorBar/Proj/mesure_card_top.v" 133 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "s_ack mesure_card_top.v(134) " "Warning: Verilog HDL net warning at mesure_card_top.v(134): created undeclared net \"s_ack\"" {  } { { "mesure_card_top.v" "" { Text "D:/VieoColorBar/Proj/mesure_card_top.v" 134 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "V_sig_vga mesure_card_top.v(146) " "Warning: Verilog HDL net warning at mesure_card_top.v(146): created undeclared net \"V_sig_vga\"" {  } { { "mesure_card_top.v" "" { Text "D:/VieoColorBar/Proj/mesure_card_top.v" 146 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "blank_PAL mesure_card_top.v(201) " "Warning: Verilog HDL net warning at mesure_card_top.v(201): created undeclared net \"blank_PAL\"" {  } { { "mesure_card_top.v" "" { Text "D:/VieoColorBar/Proj/mesure_card_top.v" 201 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mesure_card_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mesure_card_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 mesure_card_top " "Info: Found entity 1: mesure_card_top" {  } { { "mesure_card_top.v" "" { Text "D:/VieoColorBar/Proj/mesure_card_top.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Params.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file Params.v" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2k_8to512_32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram2k_8to512_32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram2k_8to512_32 " "Info: Found entity 1: ram2k_8to512_32" {  } { { "ram2k_8to512_32.v" "" { Text "D:/VieoColorBar/Proj/ram2k_8to512_32.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram512_32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram512_32.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram512_32 " "Info: Found entity 1: ram512_32" {  } { { "ram512_32.v" "" { Text "D:/VieoColorBar/Proj/ram512_32.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "receive_pal.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file receive_pal.v" { { "Info" "ISGN_ENTITY_NAME" "1 receiver_pal " "Info: Found entity 1: receiver_pal" {  } { { "receive_pal.v" "" { Text "D:/VieoColorBar/Proj/receive_pal.v" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0p392_Cb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom0p392_Cb.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0p392_Cb " "Info: Found entity 1: rom0p392_Cb" {  } { { "rom0p392_Cb.v" "" { Text "D:/VieoColorBar/Proj/rom0p392_Cb.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0p813_Cr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom0p813_Cr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0p813_Cr " "Info: Found entity 1: rom0p813_Cr" {  } { { "rom0p813_Cr.v" "" { Text "D:/VieoColorBar/Proj/rom0p813_Cr.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom1p164_Y.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom1p164_Y.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom1p164_Y " "Info: Found entity 1: rom1p164_Y" {  } { { "rom1p164_Y.v" "" { Text "D:/VieoColorBar/Proj/rom1p164_Y.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom1p596_Cr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom1p596_Cr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom1p596_Cr " "Info: Found entity 1: rom1p596_Cr" {  } { { "rom1p596_Cr.v" "" { Text "D:/VieoColorBar/Proj/rom1p596_Cr.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom2p017_Cb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rom2p017_Cb.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom2p017_Cb " "Info: Found entity 1: rom2p017_Cb" {  } { { "rom2p017_Cb.v" "" { Text "D:/VieoColorBar/Proj/rom2p017_Cb.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdr_data_path.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdr_data_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_data_path " "Info: Found entity 1: sdr_data_path" {  } { { "sdr_data_path.v" "" { Text "D:/VieoColorBar/Proj/sdr_data_path.v" 19 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "ref_ack sdr_sdram.v(116) " "Warning: Verilog HDL net warning at sdr_sdram.v(116): created undeclared net \"ref_ack\"" {  } { { "sdr_sdram.v" "" { Text "D:/VieoColorBar/Proj/sdr_sdram.v" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "cm_ack sdr_sdram.v(117) " "Warning: Verilog HDL net warning at sdr_sdram.v(117): created undeclared net \"cm_ack\"" {  } { { "sdr_sdram.v" "" { Text "D:/VieoColorBar/Proj/sdr_sdram.v" 117 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "ref_req sdr_sdram.v(130) " "Warning: Verilog HDL net warning at sdr_sdram.v(130): created undeclared net \"ref_req\"" {  } { { "sdr_sdram.v" "" { Text "D:/VieoColorBar/Proj/sdr_sdram.v" 130 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram.v(192) " "Warning: (10273) Verilog HDL warning at sdr_sdram.v(192): extended using \"x\" or \"z\"" {  } { { "sdr_sdram.v" "" { Text "D:/VieoColorBar/Proj/sdr_sdram.v" 192 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram.v(193) " "Warning: (10273) Verilog HDL warning at sdr_sdram.v(193): extended using \"x\" or \"z\"" {  } { { "sdr_sdram.v" "" { Text "D:/VieoColorBar/Proj/sdr_sdram.v" 193 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram.v(194) " "Warning: (10273) Verilog HDL warning at sdr_sdram.v(194): extended using \"x\" or \"z\"" {  } { { "sdr_sdram.v" "" { Text "D:/VieoColorBar/Proj/sdr_sdram.v" 194 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sdr_sdram.v(195) " "Warning: (10273) Verilog HDL warning at sdr_sdram.v(195): extended using \"x\" or \"z\"" {  } { { "sdr_sdram.v" "" { Text "D:/VieoColorBar/Proj/sdr_sdram.v" 195 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdr_sdram.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sdr_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_sdram " "Info: Found entity 1: sdr_sdram" {  } { { "sdr_sdram.v" "" { Text "D:/VieoColorBar/Proj/sdr_sdram.v" 20 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sender_vga.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sender_vga.v" { { "Info" "ISGN_ENTITY_NAME" "1 sender_vga " "Info: Found entity 1: sender_vga" {  } { { "sender_vga.v" "" { Text "D:/VieoColorBar/Proj/sender_vga.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_mask.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add_mask.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_mask " "Info: Found entity 1: add_mask" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reset_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file reset_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 reset_gen " "Info: Found entity 1: reset_gen" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mask_rom.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mask_rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 mask_rom " "Info: Found entity 1: mask_rom" {  } { { "mask_rom.v" "" { Text "D:/VieoColorBar/Proj/mask_rom.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "receiver_2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file receiver_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 receiver_2 " "Info: Found entity 1: receiver_2" {  } { { "receiver_2.v" "" { Text "D:/VieoColorBar/Proj/receiver_2.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "receiver.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file receiver.v" { { "Info" "ISGN_ENTITY_NAME" "1 receiver " "Info: Found entity 1: receiver" {  } { { "receiver.v" "" { Text "D:/VieoColorBar/Proj/receiver.v" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Led_run.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Led_run.v" { { "Info" "ISGN_ENTITY_NAME" "1 Led_run " "Info: Found entity 1: Led_run" {  } { { "Led_run.v" "" { Text "D:/VieoColorBar/Proj/Led_run.v" 1 -1 0 } }  } 0}  } {  } 0}