altsyncram_3f92.tdf

来自「filter,很不错,大家可以看以下」· TDF 代码 · 共 1,162 行 · 第 1/3 页

TDF
1,162 行
字号
123
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 98304,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 102399,
			PORT_A_LOGICAL_RAM_DEPTH = 131072,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 98304,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 102399,
			PORT_B_LOGICAL_RAM_DEPTH = 131072,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a25 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 102400,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 106495,
			PORT_A_LOGICAL_RAM_DEPTH = 131072,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 102400,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 106495,
			PORT_B_LOGICAL_RAM_DEPTH = 131072,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a26 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 106496,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 110591,
			PORT_A_LOGICAL_RAM_DEPTH = 131072,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 106496,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 110591,
			PORT_B_LOGICAL_RAM_DEPTH = 131072,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a27 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 110592,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 114687,
			PORT_A_LOGICAL_RAM_DEPTH = 131072,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 110592,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 114687,
			PORT_B_LOGICAL_RAM_DEPTH = 131072,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a28 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 114688,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 118783,
			PORT_A_LOGICAL_RAM_DEPTH = 131072,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 114688,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 118783,
			PORT_B_LOGICAL_RAM_DEPTH = 131072,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a29 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 118784,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 122879,
			PORT_A_LOGICAL_RAM_DEPTH = 131072,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 118784,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 122879,
			PORT_B_LOGICAL_RAM_DEPTH = 131072,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a30 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 122880,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 126975,
			PORT_A_LOGICAL_RAM_DEPTH = 131072,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 122880,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 126975,
			PORT_B_LOGICAL_RAM_DEPTH = 131072,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a31 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 126976,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 131071,
			PORT_A_LOGICAL_RAM_DEPTH = 131072,
			PORT_A_LOGICAL_RAM_WIDTH = 1,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 126976,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 131071,
			PORT_B_LOGICAL_RAM_DEPTH = 131072,
			PORT_B_LOGICAL_RAM_WIDTH = 1,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[16..0]	: WIRE;
	address_b_wire[16..0]	: WIRE;

BEGIN 
	address_reg_b[].CLK = clock1;
	address_reg_b[].D = address_b[16..12];
	address_reg_b[].ENA = clocken1;
	decode2.data[4..0] = address_a_wire[16..12];
	decode2.enable = wren_a;
	mux3.data[] = ( ram_block1a[31..0].portbdataout[0..0]);
	mux3.sel[] = address_reg_b[].Q;
	ram_block1a[31..0].clk0 = clock0;
	ram_block1a[31..0].clk1 = clock1;
	ram_block1a[0].ena0 = decode2.eq[0..0];
	ram_block1a[1].ena0 = decode2.eq[1..1];
	ram_block1a[2].ena0 = decode2.eq[2..2];
	ram_block1a[3].ena0 = decode2.eq[3..3];
	ram_block1a[4].ena0 = decode2.eq[4..4];
	ram_block1a[5].ena0 = decode2.eq[5..5];
	ram_block1a[6].ena0 = decode2.eq[6..6];
	ram_block1a[7].ena0 = decode2.eq[7..7];
	ram_block1a[8].ena0 = decode2.eq[8..8];
	ram_block1a[9].ena0 = decode2.eq[9..9];
	ram_block1a[10].ena0 = decode2.eq[10..10];
	ram_block1a[11].ena0 = decode2.eq[11..11];
	ram_block1a[12].ena0 = decode2.eq[12..12];
	ram_block1a[13].ena0 = decode2.eq[13..13];
	ram_block1a[14].ena0 = decode2.eq[14..14];
	ram_block1a[15].ena0 = decode2.eq[15..15];
	ram_block1a[16].ena0 = decode2.eq[16..16];
	ram_block1a[17].ena0 = decode2.eq[17..17];
	ram_block1a[18].ena0 = decode2.eq[18..18];
	ram_block1a[19].ena0 = decode2.eq[19..19];
	ram_block1a[20].ena0 = decode2.eq[20..20];
	ram_block1a[21].ena0 = decode2.eq[21..21];
	ram_block1a[22].ena0 = decode2.eq[22..22];
	ram_block1a[23].ena0 = decode2.eq[23..23];
	ram_block1a[24].ena0 = decode2.eq[24..24];
	ram_block1a[25].ena0 = decode2.eq[25..25];
	ram_block1a[26].ena0 = decode2.eq[26..26];
	ram_block1a[27].ena0 = decode2.eq[27..27];
	ram_block1a[28].ena0 = decode2.eq[28..28];
	ram_block1a[29].ena0 = decode2.eq[29..29];
	ram_block1a[30].ena0 = decode2.eq[30..30];
	ram_block1a[31].ena0 = decode2.eq[31..31];
	ram_block1a[31..0].ena1 = clocken1;
	ram_block1a[0].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[1].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[2].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[3].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[4].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[5].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[6].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[7].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[8].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[9].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[10].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[11].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[12].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[13].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[14].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[15].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[16].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[17].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[18].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[19].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[20].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[21].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[22].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[23].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[24].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[25].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[26].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[27].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[28].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[29].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[30].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[31].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[0..0]);
	ram_block1a[2].portadatain[] = ( data_a[0..0]);
	ram_block1a[3].portadatain[] = ( data_a[0..0]);
	ram_block1a[4].portadatain[] = ( data_a[0..0]);
	ram_block1a[5].portadatain[] = ( data_a[0..0]);
	ram_block1a[6].portadatain[] = ( data_a[0..0]);
	ram_block1a[7].portadatain[] = ( data_a[0..0]);
	ram_block1a[8].portadatain[] = ( data_a[0..0]);
	ram_block1a[9].portadatain[] = ( data_a[0..0]);
	ram_block1a[10].portadatain[] = ( data_a[0..0]);
	ram_block1a[11].portadatain[] = ( data_a[0..0]);
	ram_block1a[12].portadatain[] = ( data_a[0..0]);
	ram_block1a[13].portadatain[] = ( data_a[0..0]);
	ram_block1a[14].portadatain[] = ( data_a[0..0]);
	ram_block1a[15].portadatain[] = ( data_a[0..0]);
	ram_block1a[16].portadatain[] = ( data_a[0..0]);
	ram_block1a[17].portadatain[] = ( data_a[0..0]);
	ram_block1a[18].portadatain[] = ( data_a[0..0]);
	ram_block1a[19].portadatain[] = ( data_a[0..0]);
	ram_block1a[20].portadatain[] = ( data_a[0..0]);
	ram_block1a[21].portadatain[] = ( data_a[0..0]);
	ram_block1a[22].portadatain[] = ( data_a[0..0]);
	ram_block1a[23].portadatain[] = ( data_a[0..0]);
	ram_block1a[24].portadatain[] = ( data_a[0..0]);
	ram_block1a[25].portadatain[] = ( data_a[0..0]);
	ram_block1a[26].portadatain[] = ( data_a[0..0]);
	ram_block1a[27].portadatain[] = ( data_a[0..0]);
	ram_block1a[28].portadatain[] = ( data_a[0..0]);
	ram_block1a[29].portadatain[] = ( data_a[0..0]);
	ram_block1a[30].portadatain[] = ( data_a[0..0]);
	ram_block1a[31].portadatain[] = ( data_a[0..0]);
	ram_block1a[31..0].portawe = B"11111111111111111111111111111111";
	ram_block1a[0].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[1].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[2].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[3].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[4].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[5].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[6].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[7].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[8].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[9].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[10].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[11].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[12].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[13].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[14].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[15].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[16].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[17].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[18].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[19].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[20].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[21].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[22].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[23].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[24].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[25].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[26].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[27].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[28].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[29].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[30].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[31].portbaddr[] = ( address_b_wire[11..0]);
	ram_block1a[31..0].portbrewe = B"11111111111111111111111111111111";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = mux3.result[];
END;
--VALID FILE
123

altsyncram_3f92.tdf - 源码说明

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