altsyncram_di92.tdf

来自「filter,很不错,大家可以看以下」· TDF 代码 · 共 1,850 行 · 第 1/5 页

TDF
1,850 行
字号
12345
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 19,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 28,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a48 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 28,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 20,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 28,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a49 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 28,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 21,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 28,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a50 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 28,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 22,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 28,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a51 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 28,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 23,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 28,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a52 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 28,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 24,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 28,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a53 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 28,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 25,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 28,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a54 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 28,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 26,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 28,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a55 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 28,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 27,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 28,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[12..0]	: WIRE;
	address_b_wire[12..0]	: WIRE;

BEGIN 
	address_reg_b[].CLK = clock1;
	address_reg_b[].D = address_b[12..12];
	address_reg_b[].ENA = clocken1;
	decode2.data[0..0] = address_a_wire[12..12];
	decode2.enable = wren_a;
	mux3.data[] = ( ram_block1a[55..0].portbdataout[0..0]);
	mux3.sel[] = address_reg_b[].Q;
	ram_block1a[55..0].clk0 = clock0;
	ram_block1a[55..0].clk1 = clock1;
	ram_block1a[0].ena0 = decode2.eq[0..0];
	ram_block1a[1].ena0 = decode2.eq[0..0];
	ram_block1a[2].ena0 = decode2.eq[0..0];
	ram_block1a[3].ena0 = decode2.eq[0..0];
	ram_block1a[4].ena0 = decode2.eq[0..0];
	ram_block1a[5].ena0 = decode2.eq[0..0];
	ram_block1a[6].ena0 = decode2.eq[0..0];
	ram_block1a[7].ena0 = decode2.eq[0..0];
	ram_block1a[8].ena0 = decode2.eq[0..0];
	ram_block1a[9].ena0 = decode2.eq[0..0];
	ram_block1a[10].ena0 = decode2.eq[0..0];
	ram_block1a[11].ena0 = decode2.eq[0..0];
	ram_block1a[12].ena0 = decode2.eq[0..0];
	ram_block1a[13].ena0 = decode2.eq[0..0];
	ram_block1a[14].ena0 = decode2.eq[0..0];
	ram_block1a[15].ena0 = decode2.eq[0..0];
	ram_block1a[16].ena0 = decode2.eq[0..0];
	ram_block1a[17].ena0 = decode2.eq[0..0];
	ram_block1a[18].ena0 = decode2.eq[0..0];
	ram_block1a[19].ena0 = decode2.eq[0..0];
	ram_block1a[20].ena0 = decode2.eq[0..0];
	ram_block1a[21].ena0 = decode2.eq[0..0];
	ram_block1a[22].ena0 = decode2.eq[0..0];
	ram_block1a[23].ena0 = decode2.eq[0..0];
	ram_block1a[24].ena0 = decode2.eq[0..0];
	ram_block1a[25].ena0 = decode2.eq[0..0];
	ram_block1a[26].ena0 = decode2.eq[0..0];
	ram_block1a[27].ena0 = decode2.eq[0..0];
	ram_block1a[28].ena0 = decode2.eq[1..1];
	ram_block1a[29].ena0 = decode2.eq[1..1];
	ram_block1a[30].ena0 = decode2.eq[1..1];
	ram_block1a[31].ena0 = decode2.eq[1..1];
	ram_block1a[32].ena0 = decode2.eq[1..1];
	ram_block1a[33].ena0 = decode2.eq[1..1];
	ram_block1a[34].ena0 = decode2.eq[1..1];
	ram_block1a[35].ena0 = decode2.eq[1..1];
	ram_block1a[36].ena0 = decode2.eq[1..1];
	ram_block1a[37].ena0 = decode2.eq[1..1];
	ram_block1a[38].ena0 = decode2.eq[1..1];
	ram_block1a[39].ena0 = decode2.eq[1..1];
	ram_block1a[40].ena0 = decode2.eq[1..1];
	ram_block1a[41].ena0 = decode2.eq[1..1];
	ram_block1a[42].ena0 = decode2.eq[1..1];
	ram_block1a[43].ena0 = decode2.eq[1..1];
	ram_block1a[44].ena0 = decode2.eq[1..1];
	ram_block1a[45].ena0 = decode2.eq[1..1];
	ram_block1a[46].ena0 = decode2.eq[1..1];
	ram_block1a[47].ena0 = decode2.eq[1..1];
	ram_block1a[48].ena0 = decode2.eq[1..1];
	ram_block1a[49].ena0 = decode2.eq[1..1];
	ram_block1a[50].ena0 = decode2.eq[1..1];
	ram_block1a[51].ena0 = decode2.eq[1..1];
	ram_block1a[52].ena0 = decode2.eq[1..1];
	ram_block1a[53].ena0 = decode2.eq[1..1];
	ram_block1a[54].ena0 = decode2.eq[1..1];
	ram_block1a[55].ena0 = decode2.eq[1..1];
	ram_block1a[55..0].ena1 = clocken1;
	ram_block1a[0].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[1].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[2].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[3].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[4].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[5].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[6].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[7].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[8].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[9].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[10].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[11].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[12].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[13].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[14].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[15].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[16].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[17].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[18].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[19].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[20].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[21].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[22].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[23].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[24].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[25].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[26].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[27].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[28].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[29].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[30].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[31].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[32].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[33].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[34].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[35].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[36].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[37].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[38].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[39].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[40].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[41].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[42].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[43].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[44].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[45].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[46].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[
12345

altsyncram_di92.tdf - 源码说明

本页面展示了「filter,很不错,大家可以看以下」中的 altsyncram_di92.tdf 源码文件，采用 TDF 编程语言编写，共 1,850 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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