decode_nga.tdf

来自「filter,很不错,大家可以看以下」· TDF 代码 · 共 64 行

--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_DECODES=8 LPM_WIDTH=3 data enable eq
--VERSION_BEGIN 4.2 cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
--  partner, remains with Altera, the megafunction partner, or their respective
--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.



--synthesis_resources = lut 8 
SUBDESIGN decode_nga
( 
	data[2..0]	:	input;
	enable	:	input;
	eq[7..0]	:	output;
) 
VARIABLE 
	data_wire[2..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[7..0]	: WIRE;
	eq_wire[7..0]	: WIRE;
	w_anode404w[3..0]	: WIRE;
	w_anode421w[3..0]	: WIRE;
	w_anode431w[3..0]	: WIRE;
	w_anode441w[3..0]	: WIRE;
	w_anode451w[3..0]	: WIRE;
	w_anode461w[3..0]	: WIRE;
	w_anode471w[3..0]	: WIRE;
	w_anode481w[3..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[7..0] = eq_wire[7..0];
	eq_wire[] = ( w_anode481w[3..3], w_anode471w[3..3], w_anode461w[3..3], w_anode451w[3..3], w_anode441w[3..3], w_anode431w[3..3], w_anode421w[3..3], w_anode404w[3..3]);
	w_anode404w[] = ( (w_anode404w[2..2] & (! data_wire[2..2])), (w_anode404w[1..1] & (! data_wire[1..1])), (w_anode404w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode421w[] = ( (w_anode421w[2..2] & (! data_wire[2..2])), (w_anode421w[1..1] & (! data_wire[1..1])), (w_anode421w[0..0] & data_wire[0..0]), enable_wire);
	w_anode431w[] = ( (w_anode431w[2..2] & (! data_wire[2..2])), (w_anode431w[1..1] & data_wire[1..1]), (w_anode431w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode441w[] = ( (w_anode441w[2..2] & (! data_wire[2..2])), (w_anode441w[1..1] & data_wire[1..1]), (w_anode441w[0..0] & data_wire[0..0]), enable_wire);
	w_anode451w[] = ( (w_anode451w[2..2] & data_wire[2..2]), (w_anode451w[1..1] & (! data_wire[1..1])), (w_anode451w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode461w[] = ( (w_anode461w[2..2] & data_wire[2..2]), (w_anode461w[1..1] & (! data_wire[1..1])), (w_anode461w[0..0] & data_wire[0..0]), enable_wire);
	w_anode471w[] = ( (w_anode471w[2..2] & data_wire[2..2]), (w_anode471w[1..1] & data_wire[1..1]), (w_anode471w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode481w[] = ( (w_anode481w[2..2] & data_wire[2..2]), (w_anode481w[1..1] & data_wire[1..1]), (w_anode481w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE