i2c_altera.hif

来自「filter,很不错,大家可以看以下」· HIF 代码 · 共 5,029 行 · 第 1/5 页

HIF
5,029 行
字号
12345
SUBADDR
32'b00000000000000000000000000000101
PARAMETER_UNKNOWN
USR
SUBADDR_ACK
32'b00000000000000000000000000000110
PARAMETER_UNKNOWN
USR
DATA
32'b00000000000000000000000000000111
PARAMETER_UNKNOWN
USR
DATA_ACK
32'b00000000000000000000000000001000
PARAMETER_UNKNOWN
USR
GEN_P
32'b00000000000000000000000000001001
PARAMETER_UNKNOWN
USR
P_WAIT
32'b00000000000000000000000000001010
PARAMETER_UNKNOWN
USR
IDLE
32'b00000000000000000000000000001011
PARAMETER_UNKNOWN
USR
I2C_W_OK
32'b00000000000000000000000000001100
PARAMETER_UNKNOWN
USR
HALT
32'b00000000000000000000000000001101
PARAMETER_UNKNOWN
USR
CREATE_CHIP_RST
32'b00000000000000000000000000001110
PARAMETER_UNKNOWN
USR
}
# hierarchies {
i2c_cmd:inst
}
# end
# entity
SAA_ROM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SAA_ROM.v
1134668258
7
# storage
db|I2C_ALTERA.(19).cnf
db|I2C_ALTERA.(19).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SAA_ROM:inst2
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|I2C_ALTERA.(20).cnf
db|I2C_ALTERA.(20).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
saa7113.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_5qp
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
clock0
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
d:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
altsyncram_5qp
# case_insensitive
# source_file
db|altsyncram_5qp.tdf
1151488550
6
# storage
db|I2C_ALTERA.(21).cnf
db|I2C_ALTERA.(21).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# memory_file {
saa7113.mif
1118835142
}
# hierarchies {
SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated
}
# end
# entity
i2c_cmd_7128
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
i2c_cmd_7128.v
1118834572
7
# storage
db|I2C_ALTERA.(22).cnf
db|I2C_ALTERA.(22).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
GEN_S
00000000000000000000000000000001
PARAMETER_UNKNOWN
USR
S_WAIT
00000000000000000000000000000010
PARAMETER_UNKNOWN
USR
SUBADDR
00000000000000000000000000000101
PARAMETER_UNKNOWN
USR
SUBADDR_ACK
00000000000000000000000000000110
PARAMETER_UNKNOWN
USR
DATA
00000000000000000000000000000111
PARAMETER_UNKNOWN
USR
DATA_ACK
00000000000000000000000000001000
PARAMETER_UNKNOWN
USR
GEN_P
00000000000000000000000000001001
PARAMETER_UNKNOWN
USR
P_WAIT
00000000000000000000000000001010
PARAMETER_UNKNOWN
USR
IDLE
00000000000000000000000000001011
PARAMETER_UNKNOWN
USR
I2C_W_OK
00000000000000000000000000001100
PARAMETER_UNKNOWN
USR
HALT
00000000000000000000000000001101
PARAMETER_UNKNOWN
USR
CREATE_CHIP_RST
00000000000000000000000000001110
PARAMETER_UNKNOWN
USR
}
# hierarchies {
i2c_cmd_7128:inst17
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|I2C_ALTERA.(24).cnf
db|I2C_ALTERA.(24).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
saa7121.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_slr
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
clock0
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
d:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
add_mask
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
add_mask.v
1134313282
7
# storage
db|I2C_ALTERA.(26).cnf
db|I2C_ALTERA.(26).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
MASK_ROW_TOP
0000110010
PARAMETER_BIN
USR
MASK_ROW_BOTTOM
0001010000
PARAMETER_BIN
USR
}
# hierarchies {
add_mask:inst22
}
# end
# entity
mask_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
mask_rom.v
1147939164
7
# storage
db|I2C_ALTERA.(27).cnf
db|I2C_ALTERA.(27).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
add_mask:inst22|mask_rom:mask_rom0
}
# end
# entity
altsyncram
# case_insensitive
# source_file
d:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|I2C_ALTERA.(28).cnf
db|I2C_ALTERA.(28).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
1
PARAMETER_DEC
USR
WIDTHAD_A
14
PARAMETER_DEC
USR
NUMWORDS_A
16384
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
mask_hseda.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_j1t
PARAMETER_UNKNOWN
USR
}
# used_port {
aclr0
aclr1
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
addressstall_a
addressstall_b
byteena_a
byteena_b
clock0
clock1
clocken0
clocken1
data_a
data_b
q_a
rden_b
wren_a
wren_b
}
# include_file {
d:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
d:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
d:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
d:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
d:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
d:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
d:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
d:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
d:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
d:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
altsyncram_j1t
# case_insensitive
# source_file
db|altsyncram_j1t.tdf
1151488552
6
# storage
db|I2C_ALTERA.(29).cnf
db|I2C_ALTERA.(29).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
12345

i2c_altera.hif - 源码说明

本页面展示了「filter,很不错,大家可以看以下」中的 i2c_altera.hif 源码文件，采用 HIF 编程语言编写，共 5,029 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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