i2c_altera.fit.qmsg

filter,很不错,大家可以看以下

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.966 ns register memory " "Info: Estimated most critical path is register to memory delay of 0.966 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_cmd:inst\|rom_addr\[5\] 1 REG LAB_X15_Y14 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y14; Fanout = 14; REG Node = 'i2c_cmd:inst\|rom_addr\[5\]'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { i2c_cmd:inst|rom_addr[5] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.583 ns) + CELL(0.383 ns) 0.966 ns SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated\|ram_block1a7~porta_address_reg5 2 MEM M4K_X17_Y14 1 " "Info: 2: + IC(0.583 ns) + CELL(0.383 ns) = 0.966 ns; Loc. = M4K_X17_Y14; Fanout = 1; MEM Node = 'SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated\|ram_block1a7~porta_address_reg5'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "0.966 ns" { i2c_cmd:inst|rom_addr[5] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "db/altsyncram_5qp.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_5qp.tdf" 174 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns 39.65 % " "Info: Total cell delay = 0.383 ns ( 39.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.583 ns 60.35 % " "Info: Total interconnect delay = 0.583 ns ( 60.35 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "0.966 ns" { i2c_cmd:inst|rom_addr[5] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:09 " "Info: Fitter placement operations ending: elapsed time is 00:00:09" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 4 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 4%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Info: Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: The following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "flash_ce VCC " "Info: Pin flash_ce has VCC driving its datain port" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 752 2056 2232 768 "flash_ce" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "flash_ce" } } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { flash_ce } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { flash_ce } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "flash_oe VCC " "Info: Pin flash_oe has VCC driving its datain port" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 768 2056 2232 784 "flash_oe" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "flash_oe" } } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { flash_oe } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { flash_oe } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "flash_rw VCC " "Info: Pin flash_rw has VCC driving its datain port" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 784 2056 2232 800 "flash_rw" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "flash_rw" } } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { flash_rw } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { flash_rw } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "I2C:inst1\|SCL_reg " "Info: The following pins have the same output enable: I2C:inst1\|SCL_reg" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SCL LVTTL " "Info: Type bidirectional pin SCL uses the LVTTL I/O standard" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1104 1672 1848 1120 "SCL" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SCL" } } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { SCL } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { SCL } "NODE_NAME" } }  } 0}  } {  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "I2C:inst1\|SDA_reg " "Info: The following pins have the same output enable: I2C:inst1\|SDA_reg" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SDA LVTTL " "Info: Type bidirectional pin SDA uses the LVTTL I/O standard" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1088 1672 1848 1104 "SDA" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDA" } } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { SDA } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { SDA } "NODE_NAME" } }  } 0}  } {  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "I2C:inst10\|SCL_reg " "Info: The following pins have the same output enable: I2C:inst10\|SCL_reg" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SCL_ENC LVTTL " "Info: Type bidirectional pin SCL_ENC uses the LVTTL I/O standard" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 440 1680 1856 456 "SCL_ENC" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SCL_ENC" } } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { SCL_ENC } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { SCL_ENC } "NODE_NAME" } }  } 0}  } {  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "I2C:inst10\|SDA_reg " "Info: The following pins have the same output enable: I2C:inst10\|SDA_reg" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SDA_ENC LVTTL " "Info: Type bidirectional pin SDA_ENC uses the LVTTL I/O standard" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 424 1680 1856 440 "SDA_ENC" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SDA_ENC" } } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { SDA_ENC } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { SDA_ENC } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 14 14:55:03 2006 " "Info: Processing ended: Mon Aug 14 14:55:03 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:42 " "Info: Elapsed time: 00:00:42" {  } {  } 0}  } {  } 0}