i2c_altera.fit.qmsg

filter,很不错,大家可以看以下

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 14 14:54:22 2006 " "Info: Processing started: Mon Aug 14 14:54:22 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RVDK_Sample -c I2C_ALTERA " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off RVDK_Sample -c I2C_ALTERA" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "I2C_ALTERA EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"I2C_ALTERA\"" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "PLL:inst26\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"PLL:inst26\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL:inst26\|altpll:altpll_component\|_clk0 8 5 45 1563 " "Info: Implementing clock multiplication of 8, clock division of 5, and phase shift of 45 degrees (1563 ps) for PLL:inst26\|altpll:altpll_component\|_clk0 port" {  } {  } 0}  } { { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "PLL.v" "" { Text "D:/VieoColorBar/Proj/PLL.v" 92 -1 0 } } { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1368 536 792 1552 "inst26" "" } } } }  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "SYSCLK " "Info: Promoted signal \"SYSCLK\" to use global clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SYSCLK" } { 0 "SYSCLK" } } } } { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1424 200 368 1440 "SYSCLK" "" } } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { SYSCLK } "NODE_NAME" } }  } 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "PLL:inst26\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"PLL:inst26\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "PLL:inst26\|altpll:altpll_component\|_clk0" } { 0 "PLL:inst26\|altpll:altpll_component\|_clk0" } } } } { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1368 536 792 1552 "inst26" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { PLL:inst26|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { PLL:inst26|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PCLK Global clock in PIN 29 " "Info: Automatically promoted some destinations of signal \"PCLK\" to use Global clock in PIN 29" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ENC_CLK " "Info: Destination \"ENC_CLK\" may be non-global or may not use global clock" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1512 2000 2176 1528 "ENC_CLK" "" } } } }  } 0}  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1512 1696 1864 1528 "PCLK" "" } { 1256 2064 2144 1272 "PCLK" "" } { 1272 1736 1832 1288 "PCLK" "" } { 1248 1456 1520 1264 "PCLK" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk_gen:inst19\|clkout Global clock " "Info: Automatically promoted some destinations of signal \"clk_gen:inst19\|clkout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clk_gen:inst19\|clkout " "Info: Destination \"clk_gen:inst19\|clkout\" may be non-global or may not use global clock" {  } { { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 11 -1 0 } }  } 0}  } { { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 11 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "Led_run:inst14\|Mega_cnt\[23\] Global clock " "Info: Automatically promoted some destinations of signal \"Led_run:inst14\|Mega_cnt\[23\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Led_run:inst14\|Mega_cnt\[23\] " "Info: Destination \"Led_run:inst14\|Mega_cnt\[23\]\" may be non-global or may not use global clock" {  } { { "Led_run.v" "" { Text "D:/VieoColorBar/Proj/Led_run.v" 7 -1 0 } }  } 0}  } { { "Led_run.v" "" { Text "D:/VieoColorBar/Proj/Led_run.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset_gen:inst21\|rst_cnt\[23\] Global clock " "Info: Automatically promoted some destinations of signal \"reset_gen:inst21\|rst_cnt\[23\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[23\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[23\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[22\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[22\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[21\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[21\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[20\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[20\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[19\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[19\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[18\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[18\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[17\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[17\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[16\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[16\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[15\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[15\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reset_gen:inst21\|rst_cnt\[14\] " "Info: Destination \"reset_gen:inst21\|rst_cnt\[14\]\" may be non-global or may not use global clock" {  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "reset_gen.v" "" { Text "D:/VieoColorBar/Proj/reset_gen.v" 12 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "filter:inst8\|rst_out Global clock " "Info: Automatically promoted some destinations of signal \"filter:inst8\|rst_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd:inst\|cmd_stop " "Info: Destination \"i2c_cmd:inst\|cmd_stop\" may be non-global or may not use global clock" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd:inst\|execute " "Info: Destination \"i2c_cmd:inst\|execute\" may be non-global or may not use global clock" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd:inst\|cmd_start " "Info: Destination \"i2c_cmd:inst\|cmd_start\" may be non-global or may not use global clock" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd:inst\|cmd_send " "Info: Destination \"i2c_cmd:inst\|cmd_send\" may be non-global or may not use global clock" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd:inst\|i2c_data_t\[7\] " "Info: Destination \"i2c_cmd:inst\|i2c_data_t\[7\]\" may be non-global or may not use global clock" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 11 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd_7128:inst17\|cmd_stop " "Info: Destination \"i2c_cmd_7128:inst17\|cmd_stop\" may be non-global or may not use global clock" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd_7128:inst17\|execute " "Info: Destination \"i2c_cmd_7128:inst17\|execute\" may be non-global or may not use global clock" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd_7128:inst17\|cmd_send " "Info: Destination \"i2c_cmd_7128:inst17\|cmd_send\" may be non-global or may not use global clock" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd_7128:inst17\|i2c_data_t\[7\] " "Info: Destination \"i2c_cmd_7128:inst17\|i2c_data_t\[7\]\" may be non-global or may not use global clock" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 11 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "i2c_cmd_7128:inst17\|cmd_start " "Info: Destination \"i2c_cmd_7128:inst17\|cmd_start\" may be non-global or may not use global clock" {  } { { "i2c_cmd_7128.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd_7128.v" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "filter.v" "" { Text "D:/VieoColorBar/Proj/filter.v" 3 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "RST Global clock " "Info: Automatically promoted some destinations of signal \"RST\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "filter:inst8\|rst_out " "Info: Destination \"filter:inst8\|rst_out\" may be non-global or may not use global clock" {  } { { "filter.v" "" { Text "D:/VieoColorBar/Proj/filter.v" 3 -1 0 } }  } 0}  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 976 232 400 992 "RST" "" } { 1432 896 920 1448 "rst" "" } { 1240 1736 1832 1256 "rst" "" } { 1264 1456 1520 1280 "rst" "" } { 968 416 568 984 "rst" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "RST " "Info: Pin \"RST\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 976 232 400 992 "RST" "" } { 1432 896 920 1448 "rst" "" } { 1240 1736 1832 1256 "rst" "" } { 1264 1456 1520 1280 "rst" "" } { 968 416 568 984 "rst" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "RST" } } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { RST } "NODE_NAME" } "" } } { "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" { Floorplan "D:/VieoColorBar/Proj/I2C_ALTERA.fld" "" "" { RST } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}