i2c_altera.fit.eqn

来自「filter,很不错,大家可以看以下」· EQN 代码 · 共 1,492 行 · 第 1/5 页

M1_data4byte_pre[23] = DFFEAS(M1_data4byte_pre[23]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L661, M1_qd_dly[7], , , VCC);


--M1_add_mask_ena is add_mask:inst22|add_mask_ena at LC_X11_Y9_N2
--operation mode is normal

M1_add_mask_ena_lut_out = !M1L8 & (M1_row_cnt[5] & M1L01 # !M1_row_cnt[5] & (!M1L9));
M1_add_mask_ena = DFFEAS(M1_add_mask_ena_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--BB1_ram_block1a1 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a1 at M4K_X17_Y5
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
BB1_ram_block1a1_PORT_A_address = BUS(M1_r_ram_rab[0], M1_r_ram_rab[1], M1_r_ram_rab[2], M1_r_ram_rab[3], M1_r_ram_rab[4], M1_r_ram_rab[5], M1_r_ram_rab[6], M1_r_ram_rab[7], M1_r_ram_rab[8], M1_r_ram_rab[9], M1_r_ram_rab[10], M1_r_ram_rab[11]);
BB1_ram_block1a1_PORT_A_address_reg = DFFE(BB1_ram_block1a1_PORT_A_address, BB1_ram_block1a1_clock_0, , , BB1_ram_block1a1_clock_enable_0);
BB1_ram_block1a1_clock_0 = GLOBAL(PCLK);
BB1_ram_block1a1_clock_enable_0 = CB1L3;
BB1_ram_block1a1_PORT_A_data_out = MEMORY(, , BB1_ram_block1a1_PORT_A_address_reg, , , , , , BB1_ram_block1a1_clock_0, , BB1_ram_block1a1_clock_enable_0, , , );
BB1_ram_block1a1 = BB1_ram_block1a1_PORT_A_data_out[0];


--BB1_ram_block1a2 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a2 at M4K_X17_Y7
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
BB1_ram_block1a2_PORT_A_address = BUS(M1_r_ram_rab[0], M1_r_ram_rab[1], M1_r_ram_rab[2], M1_r_ram_rab[3], M1_r_ram_rab[4], M1_r_ram_rab[5], M1_r_ram_rab[6], M1_r_ram_rab[7], M1_r_ram_rab[8], M1_r_ram_rab[9], M1_r_ram_rab[10], M1_r_ram_rab[11]);
BB1_ram_block1a2_PORT_A_address_reg = DFFE(BB1_ram_block1a2_PORT_A_address, BB1_ram_block1a2_clock_0, , , BB1_ram_block1a2_clock_enable_0);
BB1_ram_block1a2_clock_0 = GLOBAL(PCLK);
BB1_ram_block1a2_clock_enable_0 = CB1L4;
BB1_ram_block1a2_PORT_A_data_out = MEMORY(, , BB1_ram_block1a2_PORT_A_address_reg, , , , , , BB1_ram_block1a2_clock_0, , BB1_ram_block1a2_clock_enable_0, , , );
BB1_ram_block1a2 = BB1_ram_block1a2_PORT_A_data_out[0];


--BB1_ram_block1a0 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0 at M4K_X17_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
BB1_ram_block1a0_PORT_A_address = BUS(M1_r_ram_rab[0], M1_r_ram_rab[1], M1_r_ram_rab[2], M1_r_ram_rab[3], M1_r_ram_rab[4], M1_r_ram_rab[5], M1_r_ram_rab[6], M1_r_ram_rab[7], M1_r_ram_rab[8], M1_r_ram_rab[9], M1_r_ram_rab[10], M1_r_ram_rab[11]);
BB1_ram_block1a0_PORT_A_address_reg = DFFE(BB1_ram_block1a0_PORT_A_address, BB1_ram_block1a0_clock_0, , , BB1_ram_block1a0_clock_enable_0);
BB1_ram_block1a0_clock_0 = GLOBAL(PCLK);
BB1_ram_block1a0_clock_enable_0 = CB1_w_anode25w[2];
BB1_ram_block1a0_PORT_A_data_out = MEMORY(, , BB1_ram_block1a0_PORT_A_address_reg, , , , , , BB1_ram_block1a0_clock_0, , BB1_ram_block1a0_clock_enable_0, , , );
BB1_ram_block1a0 = BB1_ram_block1a0_PORT_A_data_out[0];


--DB1L1 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~44 at LC_X20_Y7_N3
--operation mode is normal

BB1_address_reg_a[1]_qfbk = BB1_address_reg_a[1];
DB1L1 = BB1_address_reg_a[1]_qfbk & (BB1_ram_block1a2 # BB1_address_reg_a[0]) # !BB1_address_reg_a[1]_qfbk & (BB1_ram_block1a0 & !BB1_address_reg_a[0]);

--BB1_address_reg_a[1] is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|address_reg_a[1] at LC_X20_Y7_N3
--operation mode is normal

BB1_address_reg_a[1] = DFFEAS(DB1L1, GLOBAL(PCLK), VCC, , , M1_r_ram_rab[13], , , VCC);


--BB1_ram_block1a3 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a3 at M4K_X17_Y6
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
BB1_ram_block1a3_PORT_A_address = BUS(M1_r_ram_rab[0], M1_r_ram_rab[1], M1_r_ram_rab[2], M1_r_ram_rab[3], M1_r_ram_rab[4], M1_r_ram_rab[5], M1_r_ram_rab[6], M1_r_ram_rab[7], M1_r_ram_rab[8], M1_r_ram_rab[9], M1_r_ram_rab[10], M1_r_ram_rab[11]);
BB1_ram_block1a3_PORT_A_address_reg = DFFE(BB1_ram_block1a3_PORT_A_address, BB1_ram_block1a3_clock_0, , , BB1_ram_block1a3_clock_enable_0);
BB1_ram_block1a3_clock_0 = GLOBAL(PCLK);
BB1_ram_block1a3_clock_enable_0 = CB1L5;
BB1_ram_block1a3_PORT_A_data_out = MEMORY(, , BB1_ram_block1a3_PORT_A_address_reg, , , , , , BB1_ram_block1a3_clock_0, , BB1_ram_block1a3_clock_enable_0, , , );
BB1_ram_block1a3 = BB1_ram_block1a3_PORT_A_data_out[0];


--DB1L2 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~45 at LC_X20_Y7_N0
--operation mode is normal

BB1_address_reg_a[0]_qfbk = BB1_address_reg_a[0];
DB1L2 = BB1_address_reg_a[0]_qfbk & (DB1L1 & (BB1_ram_block1a3) # !DB1L1 & BB1_ram_block1a1) # !BB1_address_reg_a[0]_qfbk & (DB1L1);

--BB1_address_reg_a[0] is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|address_reg_a[0] at LC_X20_Y7_N0
--operation mode is normal

BB1_address_reg_a[0] = DFFEAS(DB1L2, GLOBAL(PCLK), VCC, , , M1_r_ram_rab[12], , , VCC);


--M1_byte_cnt[1] is add_mask:inst22|byte_cnt[1] at LC_X19_Y8_N3
--operation mode is normal

M1_byte_cnt[1]_lut_out = M1_qfv_dly & (M1_byte_cnt[1] $ M1_byte_cnt[0]);
M1_byte_cnt[1] = DFFEAS(M1_byte_cnt[1]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_byte_cnt[0] is add_mask:inst22|byte_cnt[0] at LC_X19_Y8_N8
--operation mode is normal

M1_byte_cnt[0]_lut_out = !M1_byte_cnt[0] & M1_qfv_dly;
M1_byte_cnt[0] = DFFEAS(M1_byte_cnt[0]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1L31 is add_mask:inst22|always7~0 at LC_X19_Y8_N0
--operation mode is normal

M1L31 = !M1_byte_cnt[0] & M1_qfv_dly1 & !M1_byte_cnt[1];


--M1_data4byte_pre[15] is add_mask:inst22|data4byte_pre[15] at LC_X20_Y8_N0
--operation mode is normal

M1_data4byte_pre[15]_lut_out = M1_qd_dly[7];
M1_data4byte_pre[15] = DFFEAS(M1_data4byte_pre[15]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L761, , , , );


--M1_data4byte_pre[7] is add_mask:inst22|data4byte_pre[7] at LC_X20_Y9_N8
--operation mode is normal

M1_data4byte_pre[7]_lut_out = GND;
M1_data4byte_pre[7] = DFFEAS(M1_data4byte_pre[7]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L861, M1_qd_dly[7], , , VCC);


--M1_data4byte_pre[31] is add_mask:inst22|data4byte_pre[31] at LC_X20_Y8_N8
--operation mode is normal

M1_data4byte_pre[31]_lut_out = M1_qd_dly[7];
M1_data4byte_pre[31] = DFFEAS(M1_data4byte_pre[31]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L11, , , , );


--M1_qd_dly[7] is add_mask:inst22|qd_dly[7] at LC_X13_Y8_N9
--operation mode is normal

M1_qd_dly[7]_lut_out = J1_qfv_odd & (J1_qd_dly[7]) # !J1_qfv_odd & (J1_qfv_even & J1_qd_dly[7] # !J1_qfv_even & (J1_qd_dly1[7]));
M1_qd_dly[7] = DFFEAS(M1_qd_dly[7]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--GB1_safe_q[0] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|safe_q[0] at LC_X16_Y9_N0
--operation mode is arithmetic

GB1_safe_q[0]_lut_out = !GB1_safe_q[0];
GB1_safe_q[0] = DFFEAS(GB1_safe_q[0]_lut_out, GLOBAL(PCLK), VCC, , , ~GND, , , GB1_modulus_trigger);

--GB1L3 is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|counter_cella0~COUT at LC_X16_Y9_N0
--operation mode is arithmetic

GB1L3_cout_0 = GB1_safe_q[0];
GB1L3 = CARRY(GB1L3_cout_0);

--GB1L4 is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|counter_cella0~COUTCOUT1_3 at LC_X16_Y9_N0
--operation mode is arithmetic

GB1L4_cout_1 = GB1_safe_q[0];
GB1L4 = CARRY(GB1L4_cout_1);


--GB1_safe_q[1] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|safe_q[1] at LC_X16_Y9_N1
--operation mode is arithmetic

GB1_safe_q[1]_lut_out = GB1_safe_q[1] $ (GB1L3);
GB1_safe_q[1] = DFFEAS(GB1_safe_q[1]_lut_out, GLOBAL(PCLK), VCC, , , ~GND, , , GB1_modulus_trigger);

--GB1L6 is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|counter_cella1~COUT at LC_X16_Y9_N1
--operation mode is arithmetic

GB1L6_cout_0 = !GB1L3 # !GB1_safe_q[1];
GB1L6 = CARRY(GB1L6_cout_0);

--GB1L7 is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|counter_cella1~COUTCOUT1_4 at LC_X16_Y9_N1
--operation mode is arithmetic

GB1L7_cout_1 = !GB1L4 # !GB1_safe_q[1];
GB1L7 = CARRY(GB1L7_cout_1);


--M1_qfv_dly4 is add_mask:inst22|qfv_dly4 at LC_X21_Y7_N8
--operation mode is normal

M1_qfv_dly4_lut_out = GND;
M1_qfv_dly4 = DFFEAS(M1_qfv_dly4_lut_out, GLOBAL(PCLK), VCC, , , M1_qfv_dly3, , , VCC);


--L1_rst_cnt[22] is reset_gen:inst21|rst_cnt[22] at LC_X9_Y10_N5
--operation mode is arithmetic

L1_rst_cnt[22]_carry_eqn = L1L26;
L1_rst_cnt[22]_lut_out = L1_rst_cnt[22] $ !L1_rst_cnt[22]_carry_eqn;
L1_rst_cnt[22] = DFFEAS(L1_rst_cnt[22]_lut_out, GLOBAL(PCLK), GLOBAL(RST), , !L1_rst_cnt[23], , , , );

--L1L46 is reset_gen:inst21|rst_cnt[22]~199 at LC_X9_Y10_N5
--operation mode is arithmetic

L1L46_cout_0 = L1_rst_cnt[22] & !L1L26;
L1L46 = CARRY(L1L46_cout_0);

--L1L56 is reset_gen:inst21|rst_cnt[22]~199COUT1_344 at LC_X9_Y10_N5
--operation mode is arithmetic

L1L56_cout_1 = L1_rst_cnt[22] & !L1L26;
L1L56 = CARRY(L1L56_cout_1);


--M1_data4byte_pre[14] is add_mask:inst22|data4byte_pre[14] at LC_X20_Y8_N2
--operation mode is normal

M1_data4byte_pre[14]_lut_out = GND;
M1_data4byte_pre[14] = DFFEAS(M1_data4byte_pre[14]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L761, M1_qd_dly[6], , , VCC);


--M1_data4byte_pre[22] is add_mask:inst22|data4byte_pre[22] at LC_X20_Y9_N2
--operation mode is normal

M1_data4byte_pre[22]_lut_out = GND;
M1_data4byte_pre[22] = DFFEAS(M1_data4byte_pre[22]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L661, M1_qd_dly[6], , , VCC);


--M1_data4byte_pre[6] is add_mask:inst22|data4byte_pre[6] at LC_X20_Y9_N9
--operation mode is normal

M1_data4byte_pre[6]_lut_out = GND;
M1_data4byte_pre[6] = DFFEAS(M1_data4byte_pre[6]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L861, M1_qd_dly[6], , , VCC);


--M1_data4byte_pre[30] is add_mask:inst22|data4byte_pre[30] at LC_X20_Y8_N7
--operation mode is normal

M1_data4byte_pre[30]_lut_out = GND;
M1_data4byte_pre[30] = DFFEAS(M1_data4byte_pre[30]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L11, M1_qd_dly[6], , , VCC);


--M1_qd_dly[6] is add_mask:inst22|qd_dly[6] at LC_X13_Y7_N2
--operation mode is normal

M1_qd_dly[6]_lut_out = J1_qfv_even & (J1_qd_dly[6]) # !J1_qfv_even & (J1_qfv_odd & (J1_qd_dly[6]) # !J1_qfv_odd & J1_qd_dly1[6]);
M1_qd_dly[6] = DFFEAS(M1_qd_dly[6]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--M1_data4byte_pre[21] is add_mask:inst22|data4byte_pre[21] at LC_X20_Y9_N7
--operation mode is normal

M1_data4byte_pre[21]_lut_out = M1_qd_dly[5];
M1_data4byte_pre[21] = DFFEAS(M1_data4byte_pre[21]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L661, , , , );


--M1_data4byte_pre[13] is add_mask:inst22|data4byte_pre[13] at LC_X20_Y8_N9
--operation mode is normal

M1_data4byte_pre[13]_lut_out = GND;
M1_data4byte_pre[13] = DFFEAS(M1_data4byte_pre[13]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L761, M1_qd_dly[5], , , VCC);


--M1_data4byte_pre[5] is add_mask:inst22|data4byte_pre[5] at LC_X20_Y9_N5
--operation mode is normal

M1_data4byte_pre[5]_lut_out = M1_qd_dly[5];
M1_data4byte_pre[5] = DFFEAS(M1_data4byte_pre[5]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L861, , , , );


--M1_data4byte_pre[29] is add_mask:inst22|data4byte_pre[29] at LC_X20_Y8_N5
--operation mode is normal

M1_data4byte_pre[29]_lut_out = GND;
M1_data4byte_pre[29] = DFFEAS(M1_data4byte_pre[29]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L11, M1_qd_dly[5], , , VCC);


--M1_qd_dly[5] is add_mask:inst22|qd_dly[5] at LC_X13_Y8_N8
--operation mode is normal

M1_qd_dly[5]_lut_out = J1_qfv_odd & (J1_qd_dly[5]) # !J1_qfv_odd & (J1_qfv_even & J1_qd_dly[5] # !J1_qfv_even & (J1_qd_dly1[5]));
M1_qd_dly[5] = DFFEAS(M1_qd_dly[5]_lut_out, GLOBAL(PCLK), VCC, , , , , , );


--M1_data4byte_pre[12] is add_mask:inst22|data4byte_pre[12] at LC_X20_Y8_N4
--operation mode is normal

M1_data4byte_pre[12]_lut_out = GND;
M1_data4byte_pre[12] = DFFEAS(M1_data4byte_pre[12]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L761, M1_qd_dly[4], , , VCC);


--M1_data4byte_pre[20] is add_mask:inst22|data4byte_pre[20] at LC_X20_Y9_N6
--operation mode is normal

M1_data4byte_pre[20]_lut_out = GND;
M1_data4byte_pre[20] = DFFEAS(M1_data4byte_pre[20]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L661, M1_qd_dly[4], , , VCC);


--M1_data4byte_pre[4] is add_mask:inst22|data4byte_pre[4] at LC_X20_Y9_N3
--operation mode is normal

M1_data4byte_pre[4]_lut_out = GND;
M1_data4byte_pre[4] = DFFEAS(M1_data4byte_pre[4]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L861, M1_qd_dly[4], , , VCC);


--M1_data4byte_pre[28] is add_mask:inst22|data4byte_pre[28] at LC_X20_Y8_N3
--operation mode is normal

M1_data4byte_pre[28]_lut_out = GND;
M1_data4byte_pre[28] = DFFEAS(M1_data4byte_pre[28]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L11, M1_qd_dly[4], , , VCC);


--M1_qd_dly[4] is add_mask:inst22|qd_dly[4] at LC_X13_Y8_N4
--operation mode is normal