i2c_altera.fit.eqn

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-- Copyright (C) 1991-2005 Altera Corporation
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--M1_qd_out[7] is add_mask:inst22|qd_out[7] at LC_X21_Y7_N2
--operation mode is normal

M1_qd_out[7]_lut_out = M1_qfv_dly5 & (M1L501) # !M1_qfv_dly5 & (FB1_q_b[0]);
M1_qd_out[7] = DFFEAS(M1_qd_out[7]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_qd_out[6] is add_mask:inst22|qd_out[6] at LC_X21_Y7_N5
--operation mode is normal

M1_qd_out[6]_lut_out = M1_qfv_dly5 & M1L701 # !M1_qfv_dly5 & (FB1_q_b[1]);
M1_qd_out[6] = DFFEAS(M1_qd_out[6]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_qd_out[5] is add_mask:inst22|qd_out[5] at LC_X21_Y7_N4
--operation mode is normal

M1_qd_out[5]_lut_out = M1_qfv_dly5 & (M1L901) # !M1_qfv_dly5 & FB1_q_b[2];
M1_qd_out[5] = DFFEAS(M1_qd_out[5]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_qd_out[4] is add_mask:inst22|qd_out[4] at LC_X21_Y7_N0
--operation mode is normal

M1_qd_out[4]_lut_out = M1_qfv_dly5 & (M1L111) # !M1_qfv_dly5 & FB1_q_b[3];
M1_qd_out[4] = DFFEAS(M1_qd_out[4]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_qd_out[3] is add_mask:inst22|qd_out[3] at LC_X22_Y7_N1
--operation mode is normal

M1_qd_out[3]_lut_out = M1_qfv_dly5 & M1L311 # !M1_qfv_dly5 & (FB1_q_b[4]);
M1_qd_out[3] = DFFEAS(M1_qd_out[3]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_qd_out[2] is add_mask:inst22|qd_out[2] at LC_X22_Y7_N4
--operation mode is normal

M1_qd_out[2]_lut_out = M1_qfv_dly5 & (M1L511) # !M1_qfv_dly5 & (FB1_q_b[5]);
M1_qd_out[2] = DFFEAS(M1_qd_out[2]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_qd_out[1] is add_mask:inst22|qd_out[1] at LC_X23_Y8_N7
--operation mode is normal

M1_qd_out[1]_lut_out = M1_qfv_dly5 & (M1L711) # !M1_qfv_dly5 & FB1_q_b[6];
M1_qd_out[1] = DFFEAS(M1_qd_out[1]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_qd_out[0] is add_mask:inst22|qd_out[0] at LC_X23_Y8_N4
--operation mode is normal

M1_qd_out[0]_lut_out = M1_qfv_dly5 & M1L911 # !M1_qfv_dly5 & (FB1_q_b[7]);
M1_qd_out[0] = DFFEAS(M1_qd_out[0]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--F1_led[3] is Led_run:inst14|led[3] at LC_X34_Y19_N8
--operation mode is normal

F1_led[3]_lut_out = F1_led[2] & (!F1_dir);
F1_led[3] = DFFEAS(F1_led[3]_lut_out, GLOBAL(F1_Mega_cnt[23]), GLOBAL(RST), , , , , , );


--F1_led[2] is Led_run:inst14|led[2] at LC_X34_Y19_N5
--operation mode is normal

F1_led[2]_lut_out = F1_dir & F1_led[3] # !F1_dir & (!F1_led[1]);
F1_led[2] = DFFEAS(F1_led[2]_lut_out, GLOBAL(F1_Mega_cnt[23]), GLOBAL(RST), , , , , , );


--F1_led[1] is Led_run:inst14|led[1] at LC_X34_Y19_N9
--operation mode is normal

F1_led[1]_lut_out = F1_dir & !F1_led[2] # !F1_dir & (!F1_led[0]);
F1_led[1] = DFFEAS(F1_led[1]_lut_out, GLOBAL(F1_Mega_cnt[23]), GLOBAL(RST), , , , , , );


--F1_led[0] is Led_run:inst14|led[0] at LC_X34_Y19_N2
--operation mode is normal

F1_led[0]_lut_out = !F1_led[1] & F1_dir;
F1_led[0] = DFFEAS(F1_led[0]_lut_out, GLOBAL(F1_Mega_cnt[23]), GLOBAL(RST), , , , , , );


--M1_data4byte[23] is add_mask:inst22|data4byte[23] at LC_X20_Y7_N8
--operation mode is normal

M1_data4byte[23]_lut_out = M1_data4byte_pre[23] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[23] = DFFEAS(M1_data4byte[23]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L31, , , , );


--M1_byte_cnt_out[1] is add_mask:inst22|byte_cnt_out[1] at LC_X21_Y7_N3
--operation mode is normal

M1_byte_cnt_out[1]_lut_out = M1_qfv_dly5 & (M1_byte_cnt_out[0] $ M1_byte_cnt_out[1]);
M1_byte_cnt_out[1] = DFFEAS(M1_byte_cnt_out[1]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_data4byte[15] is add_mask:inst22|data4byte[15] at LC_X20_Y7_N7
--operation mode is normal

M1_data4byte[15]_lut_out = M1_data4byte_pre[15] # M1_add_mask_ena & (DB1L2);
M1_data4byte[15] = DFFEAS(M1_data4byte[15]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L31, , , , );


--M1_byte_cnt_out[0] is add_mask:inst22|byte_cnt_out[0] at LC_X21_Y7_N7
--operation mode is normal

M1_byte_cnt_out[0]_lut_out = !M1_byte_cnt_out[0] & M1_qfv_dly5;
M1_byte_cnt_out[0] = DFFEAS(M1_byte_cnt_out[0]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , , , , , );


--M1_data4byte[7] is add_mask:inst22|data4byte[7] at LC_X20_Y7_N6
--operation mode is normal

M1_data4byte[7]_lut_out = M1_data4byte_pre[7] & (!M1_add_mask_ena # !DB1L2);
M1_data4byte[7] = DFFEAS(M1_data4byte[7]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L31, , , , );


--M1L401 is add_mask:inst22|qd_out~196 at LC_X21_Y7_N9
--operation mode is normal

M1L401 = M1_byte_cnt_out[0] & (M1_data4byte[15] # M1_byte_cnt_out[1]) # !M1_byte_cnt_out[0] & M1_data4byte[7] & (!M1_byte_cnt_out[1]);


--M1_data4byte[31] is add_mask:inst22|data4byte[31] at LC_X20_Y7_N2
--operation mode is normal

M1_data4byte[31]_lut_out = M1_data4byte_pre[31] & (!M1_add_mask_ena # !DB1L2);
M1_data4byte[31] = DFFEAS(M1_data4byte[31]_lut_out, GLOBAL(PCLK), GLOBAL(L1_rst_cnt[23]), , M1L31, , , , );


--M1L501 is add_mask:inst22|qd_out~197 at LC_X21_Y7_N1
--operation mode is normal

M1L501 = M1L401 & (M1_data4byte[31] # !M1_byte_cnt_out[1]) # !M1L401 & (M1_data4byte[23] & M1_byte_cnt_out[1]);


--FB1_q_b[0] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[0] at M4K_X17_Y9
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 4, Port A Width: 8, Port B Depth: 4, Port B Width: 8
--Port A Logical Depth: 3, Port A Logical Width: 8, Port B Logical Depth: 3, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
FB1_q_b[0]_PORT_A_data_in = BUS(M1_qd_dly[7], M1_qd_dly[6], M1_qd_dly[5], M1_qd_dly[4], M1_qd_dly[3], M1_qd_dly[2], M1_qd_dly[1], M1_qd_dly[0]);
FB1_q_b[0]_PORT_A_data_in_reg = DFFE(FB1_q_b[0]_PORT_A_data_in, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_A_address_reg = DFFE(FB1_q_b[0]_PORT_A_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_B_address_reg = DFFE(FB1_q_b[0]_PORT_B_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_write_enable = VCC;
FB1_q_b[0]_PORT_A_write_enable_reg = DFFE(FB1_q_b[0]_PORT_A_write_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_read_enable = VCC;
FB1_q_b[0]_PORT_B_read_enable_reg = DFFE(FB1_q_b[0]_PORT_B_read_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_clock_0 = GLOBAL(PCLK);
FB1_q_b[0]_PORT_B_data_out = MEMORY(FB1_q_b[0]_PORT_A_data_in_reg, , FB1_q_b[0]_PORT_A_address_reg, FB1_q_b[0]_PORT_B_address_reg, FB1_q_b[0]_PORT_A_write_enable_reg, FB1_q_b[0]_PORT_B_read_enable_reg, , , FB1_q_b[0]_clock_0, , , , , );
FB1_q_b[0]_PORT_B_data_out_reg = DFFE(FB1_q_b[0]_PORT_B_data_out, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0] = FB1_q_b[0]_PORT_B_data_out_reg[0];

--FB1_q_b[7] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[7] at M4K_X17_Y9
FB1_q_b[0]_PORT_A_data_in = BUS(M1_qd_dly[7], M1_qd_dly[6], M1_qd_dly[5], M1_qd_dly[4], M1_qd_dly[3], M1_qd_dly[2], M1_qd_dly[1], M1_qd_dly[0]);
FB1_q_b[0]_PORT_A_data_in_reg = DFFE(FB1_q_b[0]_PORT_A_data_in, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_A_address_reg = DFFE(FB1_q_b[0]_PORT_A_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_B_address_reg = DFFE(FB1_q_b[0]_PORT_B_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_write_enable = VCC;
FB1_q_b[0]_PORT_A_write_enable_reg = DFFE(FB1_q_b[0]_PORT_A_write_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_read_enable = VCC;
FB1_q_b[0]_PORT_B_read_enable_reg = DFFE(FB1_q_b[0]_PORT_B_read_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_clock_0 = GLOBAL(PCLK);
FB1_q_b[0]_PORT_B_data_out = MEMORY(FB1_q_b[0]_PORT_A_data_in_reg, , FB1_q_b[0]_PORT_A_address_reg, FB1_q_b[0]_PORT_B_address_reg, FB1_q_b[0]_PORT_A_write_enable_reg, FB1_q_b[0]_PORT_B_read_enable_reg, , , FB1_q_b[0]_clock_0, , , , , );
FB1_q_b[0]_PORT_B_data_out_reg = DFFE(FB1_q_b[0]_PORT_B_data_out, FB1_q_b[0]_clock_0, , , );
FB1_q_b[7] = FB1_q_b[0]_PORT_B_data_out_reg[7];

--FB1_q_b[6] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[6] at M4K_X17_Y9
FB1_q_b[0]_PORT_A_data_in = BUS(M1_qd_dly[7], M1_qd_dly[6], M1_qd_dly[5], M1_qd_dly[4], M1_qd_dly[3], M1_qd_dly[2], M1_qd_dly[1], M1_qd_dly[0]);
FB1_q_b[0]_PORT_A_data_in_reg = DFFE(FB1_q_b[0]_PORT_A_data_in, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_A_address_reg = DFFE(FB1_q_b[0]_PORT_A_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_B_address_reg = DFFE(FB1_q_b[0]_PORT_B_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_write_enable = VCC;
FB1_q_b[0]_PORT_A_write_enable_reg = DFFE(FB1_q_b[0]_PORT_A_write_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_read_enable = VCC;
FB1_q_b[0]_PORT_B_read_enable_reg = DFFE(FB1_q_b[0]_PORT_B_read_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_clock_0 = GLOBAL(PCLK);
FB1_q_b[0]_PORT_B_data_out = MEMORY(FB1_q_b[0]_PORT_A_data_in_reg, , FB1_q_b[0]_PORT_A_address_reg, FB1_q_b[0]_PORT_B_address_reg, FB1_q_b[0]_PORT_A_write_enable_reg, FB1_q_b[0]_PORT_B_read_enable_reg, , , FB1_q_b[0]_clock_0, , , , , );
FB1_q_b[0]_PORT_B_data_out_reg = DFFE(FB1_q_b[0]_PORT_B_data_out, FB1_q_b[0]_clock_0, , , );
FB1_q_b[6] = FB1_q_b[0]_PORT_B_data_out_reg[6];

--FB1_q_b[5] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[5] at M4K_X17_Y9
FB1_q_b[0]_PORT_A_data_in = BUS(M1_qd_dly[7], M1_qd_dly[6], M1_qd_dly[5], M1_qd_dly[4], M1_qd_dly[3], M1_qd_dly[2], M1_qd_dly[1], M1_qd_dly[0]);
FB1_q_b[0]_PORT_A_data_in_reg = DFFE(FB1_q_b[0]_PORT_A_data_in, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_A_address_reg = DFFE(FB1_q_b[0]_PORT_A_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_B_address_reg = DFFE(FB1_q_b[0]_PORT_B_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_write_enable = VCC;
FB1_q_b[0]_PORT_A_write_enable_reg = DFFE(FB1_q_b[0]_PORT_A_write_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_read_enable = VCC;
FB1_q_b[0]_PORT_B_read_enable_reg = DFFE(FB1_q_b[0]_PORT_B_read_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_clock_0 = GLOBAL(PCLK);
FB1_q_b[0]_PORT_B_data_out = MEMORY(FB1_q_b[0]_PORT_A_data_in_reg, , FB1_q_b[0]_PORT_A_address_reg, FB1_q_b[0]_PORT_B_address_reg, FB1_q_b[0]_PORT_A_write_enable_reg, FB1_q_b[0]_PORT_B_read_enable_reg, , , FB1_q_b[0]_clock_0, , , , , );
FB1_q_b[0]_PORT_B_data_out_reg = DFFE(FB1_q_b[0]_PORT_B_data_out, FB1_q_b[0]_clock_0, , , );
FB1_q_b[5] = FB1_q_b[0]_PORT_B_data_out_reg[5];

--FB1_q_b[4] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[4] at M4K_X17_Y9
FB1_q_b[0]_PORT_A_data_in = BUS(M1_qd_dly[7], M1_qd_dly[6], M1_qd_dly[5], M1_qd_dly[4], M1_qd_dly[3], M1_qd_dly[2], M1_qd_dly[1], M1_qd_dly[0]);
FB1_q_b[0]_PORT_A_data_in_reg = DFFE(FB1_q_b[0]_PORT_A_data_in, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_A_address_reg = DFFE(FB1_q_b[0]_PORT_A_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_B_address_reg = DFFE(FB1_q_b[0]_PORT_B_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_write_enable = VCC;
FB1_q_b[0]_PORT_A_write_enable_reg = DFFE(FB1_q_b[0]_PORT_A_write_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_read_enable = VCC;
FB1_q_b[0]_PORT_B_read_enable_reg = DFFE(FB1_q_b[0]_PORT_B_read_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_clock_0 = GLOBAL(PCLK);
FB1_q_b[0]_PORT_B_data_out = MEMORY(FB1_q_b[0]_PORT_A_data_in_reg, , FB1_q_b[0]_PORT_A_address_reg, FB1_q_b[0]_PORT_B_address_reg, FB1_q_b[0]_PORT_A_write_enable_reg, FB1_q_b[0]_PORT_B_read_enable_reg, , , FB1_q_b[0]_clock_0, , , , , );
FB1_q_b[0]_PORT_B_data_out_reg = DFFE(FB1_q_b[0]_PORT_B_data_out, FB1_q_b[0]_clock_0, , , );
FB1_q_b[4] = FB1_q_b[0]_PORT_B_data_out_reg[4];

--FB1_q_b[3] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[3] at M4K_X17_Y9
FB1_q_b[0]_PORT_A_data_in = BUS(M1_qd_dly[7], M1_qd_dly[6], M1_qd_dly[5], M1_qd_dly[4], M1_qd_dly[3], M1_qd_dly[2], M1_qd_dly[1], M1_qd_dly[0]);
FB1_q_b[0]_PORT_A_data_in_reg = DFFE(FB1_q_b[0]_PORT_A_data_in, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_A_address_reg = DFFE(FB1_q_b[0]_PORT_A_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_B_address_reg = DFFE(FB1_q_b[0]_PORT_B_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_write_enable = VCC;
FB1_q_b[0]_PORT_A_write_enable_reg = DFFE(FB1_q_b[0]_PORT_A_write_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_read_enable = VCC;
FB1_q_b[0]_PORT_B_read_enable_reg = DFFE(FB1_q_b[0]_PORT_B_read_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_clock_0 = GLOBAL(PCLK);
FB1_q_b[0]_PORT_B_data_out = MEMORY(FB1_q_b[0]_PORT_A_data_in_reg, , FB1_q_b[0]_PORT_A_address_reg, FB1_q_b[0]_PORT_B_address_reg, FB1_q_b[0]_PORT_A_write_enable_reg, FB1_q_b[0]_PORT_B_read_enable_reg, , , FB1_q_b[0]_clock_0, , , , , );
FB1_q_b[0]_PORT_B_data_out_reg = DFFE(FB1_q_b[0]_PORT_B_data_out, FB1_q_b[0]_clock_0, , , );
FB1_q_b[3] = FB1_q_b[0]_PORT_B_data_out_reg[3];

--FB1_q_b[2] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[2] at M4K_X17_Y9
FB1_q_b[0]_PORT_A_data_in = BUS(M1_qd_dly[7], M1_qd_dly[6], M1_qd_dly[5], M1_qd_dly[4], M1_qd_dly[3], M1_qd_dly[2], M1_qd_dly[1], M1_qd_dly[0]);
FB1_q_b[0]_PORT_A_data_in_reg = DFFE(FB1_q_b[0]_PORT_A_data_in, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_A_address_reg = DFFE(FB1_q_b[0]_PORT_A_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_B_address_reg = DFFE(FB1_q_b[0]_PORT_B_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_write_enable = VCC;
FB1_q_b[0]_PORT_A_write_enable_reg = DFFE(FB1_q_b[0]_PORT_A_write_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_read_enable = VCC;
FB1_q_b[0]_PORT_B_read_enable_reg = DFFE(FB1_q_b[0]_PORT_B_read_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_clock_0 = GLOBAL(PCLK);
FB1_q_b[0]_PORT_B_data_out = MEMORY(FB1_q_b[0]_PORT_A_data_in_reg, , FB1_q_b[0]_PORT_A_address_reg, FB1_q_b[0]_PORT_B_address_reg, FB1_q_b[0]_PORT_A_write_enable_reg, FB1_q_b[0]_PORT_B_read_enable_reg, , , FB1_q_b[0]_clock_0, , , , , );
FB1_q_b[0]_PORT_B_data_out_reg = DFFE(FB1_q_b[0]_PORT_B_data_out, FB1_q_b[0]_clock_0, , , );
FB1_q_b[2] = FB1_q_b[0]_PORT_B_data_out_reg[2];

--FB1_q_b[1] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[1] at M4K_X17_Y9
FB1_q_b[0]_PORT_A_data_in = BUS(M1_qd_dly[7], M1_qd_dly[6], M1_qd_dly[5], M1_qd_dly[4], M1_qd_dly[3], M1_qd_dly[2], M1_qd_dly[1], M1_qd_dly[0]);
FB1_q_b[0]_PORT_A_data_in_reg = DFFE(FB1_q_b[0]_PORT_A_data_in, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_A_address_reg = DFFE(FB1_q_b[0]_PORT_A_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_B_address_reg = DFFE(FB1_q_b[0]_PORT_B_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_write_enable = VCC;
FB1_q_b[0]_PORT_A_write_enable_reg = DFFE(FB1_q_b[0]_PORT_A_write_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_read_enable = VCC;
FB1_q_b[0]_PORT_B_read_enable_reg = DFFE(FB1_q_b[0]_PORT_B_read_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_clock_0 = GLOBAL(PCLK);
FB1_q_b[0]_PORT_B_data_out = MEMORY(FB1_q_b[0]_PORT_A_data_in_reg, , FB1_q_b[0]_PORT_A_address_reg, FB1_q_b[0]_PORT_B_address_reg, FB1_q_b[0]_PORT_A_write_enable_reg, FB1_q_b[0]_PORT_B_read_enable_reg, , , FB1_q_b[0]_clock_0, , , , , );
FB1_q_b[0]_PORT_B_data_out_reg = DFFE(FB1_q_b[0]_PORT_B_data_out, FB1_q_b[0]_clock_0, , , );
FB1_q_b[1] = FB1_q_b[0]_PORT_B_data_out_reg[1];


--M1_qfv_dly5 is add_mask:inst22|qfv_dly5 at LC_X21_Y7_N6
--operation mode is normal

M1_qfv_dly5_lut_out = GND;
M1_qfv_dly5 = DFFEAS(M1_qfv_dly5_lut_out, GLOBAL(PCLK), VCC, , , M1_qfv_dly4, , , VCC);


--L1_rst_cnt[23] is reset_gen:inst21|rst_cnt[23] at LC_X9_Y10_N6
--operation mode is normal

L1_rst_cnt[23]_carry_eqn = (!L1L26 & L1L46) # (L1L26 & L1L56);
L1_rst_cnt[23]_lut_out = L1_rst_cnt[23]_carry_eqn $ L1_rst_cnt[23];
L1_rst_cnt[23] = DFFEAS(L1_rst_cnt[23]_lut_out, GLOBAL(PCLK), GLOBAL(RST), , !L1_rst_cnt[23], , , , );