led_run.v

来自「filter,很不错,大家可以看以下」· Verilog 代码 · 共 45 行

module Led_run(rst,clk,led);
input       clk,rst;
output[3:0] led;
reg   [3:0] led;

wire      clk_r;
reg[23:0] Mega_cnt;
reg       dir;
/**********Get a Slow Clock********/
always @(posedge clk or negedge rst)
begin
if(!rst)
  begin
  Mega_cnt<=0;
  end
else
  begin
  Mega_cnt<=Mega_cnt+1;
  end
end

assign clk_r = Mega_cnt[23];
/**********************************/


always @(posedge clk_r or negedge rst)
begin
  if(!rst)
     begin
     led <= 4'b0010;
     dir <= 'b0;
     end
  else  
     begin
     if((led == 4'b0100) & (!dir))
       dir <= 1;
     else 
       if((led == 4'b0010) & (dir))
            dir <= 'b0;
     led <= dir? (led >>1) : (led <<1);        
    end
end


endmodule