i2c_altera.map.rpt

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Analysis & Synthesis report for I2C_ALTERA
Mon Aug 14 14:54:18 2006
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. State Machine - |I2C_ALTERA|add_mask:inst22|STATE
 10. State Machine - |I2C_ALTERA|i2c_cmd_7128:inst17|STATE
 11. State Machine - |I2C_ALTERA|I2C:inst10|Sx
 12. State Machine - |I2C_ALTERA|I2C:inst10|Ss
 13. State Machine - |I2C_ALTERA|I2C:inst10|Sy
 14. State Machine - |I2C_ALTERA|I2C:inst10|St
 15. State Machine - |I2C_ALTERA|i2c_cmd:inst|STATE
 16. State Machine - |I2C_ALTERA|I2C:inst1|Sx
 17. State Machine - |I2C_ALTERA|I2C:inst1|Ss
 18. State Machine - |I2C_ALTERA|I2C:inst1|Sy
 19. State Machine - |I2C_ALTERA|I2C:inst1|St
 20. General Register Statistics
 21. Inverted Register Statistics
 22. Multiplexer Restructuring Statistics (Restructuring Performed)
 23. Parameter Settings for User Entity Instance: I2C:inst1
 24. Parameter Settings for User Entity Instance: I2C:inst1|div_by_n:div_by_x
 25. Parameter Settings for User Entity Instance: I2C:inst1|div_by_n:div_by_x|lpm_counter:counter
 26. Parameter Settings for User Entity Instance: I2C:inst1|div_by_n:div_by_x|lpm_compare:$00002
 27. Parameter Settings for User Entity Instance: PLL:inst26|altpll:altpll_component
 28. Parameter Settings for User Entity Instance: i2c_cmd:inst
 29. Parameter Settings for User Entity Instance: SAA_ROM:inst2|altsyncram:altsyncram_component
 30. Parameter Settings for User Entity Instance: I2C:inst10
 31. Parameter Settings for User Entity Instance: I2C:inst10|div_by_n:div_by_x
 32. Parameter Settings for User Entity Instance: I2C:inst10|div_by_n:div_by_x|lpm_counter:counter
 33. Parameter Settings for User Entity Instance: I2C:inst10|div_by_n:div_by_x|lpm_compare:$00002
 34. Parameter Settings for User Entity Instance: i2c_cmd_7128:inst17
 35. Parameter Settings for User Entity Instance: ENC_ROM:inst16|altsyncram:altsyncram_component
 36. Parameter Settings for User Entity Instance: add_mask:inst22
 37. Parameter Settings for User Entity Instance: add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component
 38. Parameter Settings for Inferred Entity Instance: add_mask:inst22|altshift_taps:qd_dly1_rtl_0
 39. altshift_taps Parameter Settings by Entity Instance
 40. Analysis & Synthesis Equations
 41. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Aug 14 14:54:18 2006         ;
; Quartus II Version          ; 5.0 Build 171 11/03/2005 SP 2 SJ Full Version ;
; Revision Name               ; I2C_ALTERA                                    ;
; Top-level Entity Name       ; I2C_ALTERA                                    ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 532                                           ;
; Total pins                  ; 35                                            ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 18,456                                        ;
; Total PLLs                  ; 1                                             ;
+-----------------------------+-----------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C6Q240C8  ;               ;
; Top-level entity name                                              ; I2C_ALTERA   ; I2C_ALTERA    ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Type of Retiming Performed During Resynthesis                      ; Full         ;               ;
; Resynthesis Optimization Effort                                    ; Normal       ;               ;
; Physical Synthesis Level for Resynthesis                           ; Normal       ;               ;
; Use Generated Physical Constraints File                            ; On           ;               ;
; Use smart compilation                                              ; Off          ; Off           ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;
; State Machine Processing                                           ; Auto         ; Auto          ;
; Extract Verilog State Machines                                     ; On           ; On            ;
; Extract VHDL State Machines                                        ; On           ; On            ;
; Add Pass-Through Logic to Inferred RAMs                            ; On           ; On            ;
; NOT Gate Push-Back                                                 ; On           ; On            ;
; Power-Up Don't Care                                                ; On           ; On            ;
; Remove Redundant Logic Cells                                       ; Off          ; Off           ;
; Remove Duplicate Registers                                         ; On           ; On            ;
; Ignore CARRY Buffers                                               ; Off          ; Off           ;
; Ignore CASCADE Buffers                                             ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off          ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off          ; Off           ;
; Ignore LCELL Buffers                                               ; Off          ; Off           ;