i2c_altera.tan.rpt

来自「filter,很不错,大家可以看以下」· RPT 代码 · 共 217 行 · 第 1/5 页

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Type                                                    ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                              ; To                                                                                                          ; From Clock                               ; To Clock                                 ; Failed Paths ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Worst-case tsu                                          ; N/A       ; None                             ; 4.821 ns                         ; PDATA[2]                                                                                                                          ; receiver:inst18|qd_dly[2]                                                                                   ;                                          ; PCLK                                     ; 0            ;
; Worst-case tco                                          ; N/A       ; None                             ; 11.715 ns                        ; I2C:inst1|SCL_reg                                                                                                                 ; SCL                                                                                                         ; SYSCLK                                   ;                                          ; 0            ;
; Worst-case tpd                                          ; N/A       ; None                             ; 12.444 ns                        ; P_VS                                                                                                                              ; ENC_VS                                                                                                      ;                                          ;                                          ; 0            ;
; Worst-case th                                           ; N/A       ; None                             ; -1.562 ns                        ; SDA_ENC                                                                                                                           ; I2C:inst10|Sh_reg[0]                                                                                        ;                                          ; SYSCLK                                   ; 0            ;
; Clock Setup: 'SYSCLK'                                   ; -5.705 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; i2c_cmd:inst|rom_addr[5]                                                                                                          ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 ; PLL:inst26|altpll:altpll_component|_clk0 ; SYSCLK                                   ; 14           ;
; Clock Setup: 'PLL:inst26|altpll:altpll_component|_clk0' ; 1.090 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; filter:inst8|rst_out                                                                                                              ; i2c_cmd:inst|i2c_data_t[7]                                                                                  ; SYSCLK                                   ; PLL:inst26|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'PCLK'                                     ; N/A       ; None                             ; 101.56 MHz ( period = 9.846 ns ) ; add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg11 ; add_mask:inst22|data4byte[8]                                                                                ; PCLK                                     ; PCLK                                     ; 0            ;
; Clock Hold: 'PLL:inst26|altpll:altpll_component|_clk0'  ; 0.822 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; i2c_cmd:inst|execute                                                                                                              ; i2c_cmd:inst|execute                                                                                        ; PLL:inst26|altpll:altpll_component|_clk0 ; PLL:inst26|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'SYSCLK'                                    ; 1.039 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; Led_run:inst14|Mega_cnt[23]                                                                                                       ; Led_run:inst14|Mega_cnt[23]                                                                                 ; SYSCLK                                   ; SYSCLK                                   ; 0            ;
; Total number of failed paths                            ;           ;                                  ;                                  ;                                                                                                                                   ;                                                                                                             ;                                          ;                                          ; 14           ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+