mesure_card_top.v

来自「filter,很不错,大家可以看以下」· Verilog 代码 · 共 233 行

module mesure_card_top(      
	clkin,             
	rst,               
    
	qd,               
	qck,
	qfv,               
           
	                     
	hsout_vga,           
	vsout_vga,           
	pixel_R,             
	pixel_G,             
	pixel_B,             
	blankout_vga,        
	                     
	                     
	dq    ,              
	sa    ,              
	ba    ,              
	cke   ,              
	cs_n  ,              
	ras_n ,              
	cas_n ,              
	we_n  ,              
	sdram_clk,           
	dqm,                           
	                               
	clk40m         
  
);
input	clkin;
input	rst;
input	[7:0]	qd;
input	qck;
input	qfv;
input	clk40m;

inout	[31:0]	dq     ;
output	[10:0]	sa     ;
output	[1:0]	ba     ;
output	cke    ;
output	cs_n;
output	ras_n;
output	cas_n;
output	we_n;
output	sdram_clk;
output	[3:0]	dqm;

output	hsout_vga;
output	vsout_vga;
output	[7:0]	pixel_R;
output	[7:0]	pixel_G;
output	[7:0]	pixel_B;
output	blankout_vga;  

assign      dqm = 4'd0;
	
assign    clk = clkin;   
wire	odd_even_sig;
wire	frame_syc;
sync_gen sync_gen0(
	.rst(rst),					
	.qd(qd),
	.clk(qck),
	
	.odd_even_sig(odd_even_sig),
	.frame_syc(frame_syc)
	);
			
wire	[7:0]	r_ram_wdb;
wire	[10:0]	r_ram_wab;
wire	[7:0]	qd,r_ram_wdb_test;
wire	qck;
wire	H_sig;
wire	V_sig;
       
wire	r_req;
wire	r_ack;
wire	r_ram_wen;

receiver_pal receiver1( 
	.rst(rst),	
	.qd(qd),
	.clk(qck),
	.qfv(qfv),
	.odd_even_in(odd_even_sig),
	          
	.r_ram_wdb(r_ram_wdb),
	.r_ram_wdb_test(r_ram_wdb_test),
	.r_ram_wab(r_ram_wab),
	.r_ram_wen(r_ram_wen),	         
	.r_req(r_req),
	.r_ack(r_ack),
	
	.start_read(start_read)  	  
	);
		
wire	[8:0]	r_ram_rab;
wire	[31:0]	r_ram_rdb;
		
ram2k_8to512_32 ram_r0( 
	.data     (r_ram_wdb)  ,
	.wren     (r_ram_wen)  ,
	.wraddress(r_ram_wab)  ,
	.rdaddress(r_ram_rab)  ,
	.wrclock  (qck)  ,
	.rdclock  (clk)  ,
	.q        (r_ram_rdb)
	);  
     	            
wire	start_send;
wire	[8:0]	s_ram_wab;
wire	[31:0]	s_ram_wdb;
wire	[2:0]	cmd        ;
wire	cmdack     ;
wire	[20:0]	addr       ;
wire	[31:0]	datain     ;
wire	[31:0]	dataout    ;
wire	vsync_vga,vsync;   
datacnl  datacnl1( 
	.clk(clk)   ,
	.rst(rst)   ,
	              
	.r_ram_rdb(r_ram_rdb),
	.r_ram_rab(r_ram_rab),
	.r_req(r_req    ),
	.r_ack(r_ack),
                    
	.s_ram_wdb(s_ram_wdb),
	.s_ram_wab(s_ram_wab),
	.s_ram_wen(s_ram_wen),
	.s_req(s_req),
	.s_ack(s_ack),
	           
	.cmd(cmd),
	.cmdack(cmdack),
	.addr(addr),
	.datain(datain),
	.dataout(dataout),
	                              
	.start_read(start_read),
	
	.start_send(start_send),
	.vsync(frame_syc),
	.vsync_vga(V_sig_vga)         
                );  
                
wire [10:0]  sa   ; 
wire [1:0]   ba   ; 
wire         cs_n ;
wire         cke  ;
wire         ras_n;
wire         cas_n;
wire         we_n ;
wire [31:0]  dq   ;  
 
sdr_sdram sdr_sdram1(
        .CLK    (clk),
        .RESET_N(rst),
        .ADDR   (addr),
        .CMD    (cmd),
        .CMDACK (cmdack),
        .DATAIN (datain),    
        .DATAOUT(dataout),

        .SA     (sa),
        .BA     (ba),
        .CS_N   (cs_n),
        .CKE    (cke),
        .RAS_N  (ras_n),
        .CAS_N  (cas_n),
        .WE_N   (we_n),
        .DQ     (dq)
        );

wire	[31:0]	s_ram_rdb_raw_vga;    
wire	[8:0]	s_ram_rab_raw_vga; 
	
ram512_32 ram_s1( 
	.data     (s_ram_wdb),
	.wren     (s_ram_wen),
	.wraddress(s_ram_wab),
	.rdaddress(s_ram_rab_raw_vga),
	.wrclock  (clk),
	.rdclock  (clk40m),
	.q        (s_ram_rdb_raw_vga)
	);     


wire	H_sig_vga,qfv_vga;
wire	[7:0]	pixel_R,pixel_G,pixel_B;
wire	blank_NTSC;
sender_vga sender_vga0(	
	.rst(rst),
	.clk(clk40m), 
                
	.hsin(H_sig_vga),
	.vsin(V_sig_vga),
	.blankin(qfv_vga),
	.blank_NTSC(blank_PAL),

	.pixel_R(pixel_R),
	.pixel_G(pixel_G),
	.pixel_B(pixel_B),
	        
	.send_ram_rdb_raw(s_ram_rdb_raw_vga),
	
	.send_ram_rab_raw(s_ram_rab_raw_vga),

	.s_req_raw(s_req),
	
        .s_ack_raw(s_ack),
        
	.hsout(hsout_vga),
	.vsout(vsout_vga),
	.blankout(blankout_vga)
	); 


vga_out vga_out0(	
	.rst(rst),
	.clk40m(clk40m),
	.hsync(H_sig_vga),
	.vsync(V_sig_vga),
	.blank(qfv_vga),
	.blank_NTSC(blank_NTSC),
	.blank_PAL(blank_PAL)
	); 

endmodule