test_frame_sync.stp

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<session jtag_chain="ByteBlasterII [LPT1]" jtag_device="@1: EP1C20 (0x020840DD)" sof_file="I2C_ALTERA.sof">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="3"/>
    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2005/12/03 12:54:10  #0">
      <clock name="P_HS" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="no" trigger_in_node="hsout_vga" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="P_VS" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="mesure_card_top:inst23|sync_gen:sync_gen0|frame_syc" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="mesure_card_top:inst23|sync_gen:sync_gen0|odd_even_sig" tap_mode="classic" type="combinatorial"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="P_VS" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="mesure_card_top:inst23|sync_gen:sync_gen0|frame_syc" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="mesure_card_top:inst23|sync_gen:sync_gen0|odd_even_sig" tap_mode="classic" type="combinatorial"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <net is_signal_inverted="no" name="mesure_card_top:inst23|sync_gen:sync_gen0|odd_even_sig"/>
          <net is_signal_inverted="no" name="P_VS"/>
          <net is_signal_inverted="no" name="mesure_card_top:inst23|sync_gen:sync_gen0|frame_syc"/>
        </data_view>
        <setup_view>
          <net is_signal_inverted="no" name="mesure_card_top:inst23|sync_gen:sync_gen0|odd_even_sig"/>
          <net is_signal_inverted="no" name="P_VS"/>
          <net is_signal_inverted="no" name="mesure_card_top:inst23|sync_gen:sync_gen0|frame_syc"/>
        </setup_view>
      </presentation>
      <trigger CRC="D83078B9" global_temp="1" is_expanded="true" name="trigger: 2005/12/03 12:54:10  #1" position="pre" segment_size="1" trigger_in="falling edge" trigger_out="active high" trigger_type="circular">
        <events>
          <level enabled="yes" type="basic">
            <op_node>
              <op_node expanded="1" left="462" top="137" type="Advanced Trigger Level Result">
                <op_node expanded="1" left="332" logical="Logical Or" name="logical_0" top="97" type="Logical Operator">
                  <op_node expanded="1" left="202" name="logical_1" selected="1" top="27" type="Logical Operator">
                    <op_node expanded="1" left="72" name="comparison_3" top="12" type="Comparison Operator">
                      <op_node bus_name="mesure_card_top:inst23|sync_gen:sync_gen0|qd" left="-58" name="bus_0" top="37" type="Bus">
                        <op_node left="-45" name="mesure_card_top:inst23|sync_gen:sync_gen0|qd[7]" top="20" type="Node"/>