sender_video.v

filter,很不错,大家可以看以下

`timescale 1ns / 1ns

module sender_video(	
	rst,						//main reset
	clk,				     	       //system clock
                
	hsin,
	vsin,
	blankin,

	pixel,
	        
	send_ram_rdb_raw,
	send_ram_rdb_mask,
	
	send_ram_rab_raw,
	send_ram_rab_mask,
               
	s_req_raw,
        s_ack_raw,
        
        s_req_mask,
        s_ack_mask,
        
        hsout,
        vsout,
        blankout
              );						


/***input and output ***/
input	rst,clk;
input	hsin,vsin,blankin;

input	[7:0]	send_ram_rdb_raw;
input	[1:0]	send_ram_rdb_mask;
input	s_ack_mask;
input	s_ack_raw;

output	[7:0]	pixel;
output	[9:0]	send_ram_rab_raw;
output	[10:0]	send_ram_rab_mask;

output	hsout,vsout,blankout;
output	s_req_raw;
output	s_req_mask;

reg	s_req_raw;
reg	[7:0]	pixel_out;


//define the dram pixels(one line)
parameter  DRAM_PIXEL    = 'd256;//H_PIXELS>>1;//'d320
//define the state machine state,using one-hot coding
parameter	IDLE     =   6'b000001,
		SEND1    =   6'b000010,
		SEND2    =   6'b000100,
		SEND3    =   6'b001000,
		SEND4    =   6'b010000,
		SEND5    =   6'b100000;

reg	hsout_reg,hsout,vsout_reg,vsout,blankout,blankout_reg;


always @ (posedge clk) begin
	hsout_reg <= hsin;
	hsout <= hsout_reg;
	
	vsout_reg <= vsin;
	vsout <= vsout_reg;
	
	blankout_reg <= blankin;	
	blankout <= blankout_reg;	
	end

	
reg	[9:0]	send_ram_rab_reg;
reg	send_ram_rab_hbit;


always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_reg <= 0;
else if(blankin) begin
	if(send_ram_rab_reg == 'd719)
		send_ram_rab_reg <= 0;
	else
		send_ram_rab_reg <= send_ram_rab_reg + 1;
	end
else
	send_ram_rab_reg <= 0;

always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_hbit <= 0;
else if(send_ram_rab_reg == 'd719)
	send_ram_rab_hbit <= ~send_ram_rab_hbit;
else if(!vsout)
	send_ram_rab_hbit <= 0;

wire	[10:0]	send_ram_rab_mask = {send_ram_rab_hbit,send_ram_rab_reg};
wire	[10:0]	send_ram_rab_raw = send_ram_rab_reg;

always @ (posedge clk or negedge rst)
if(!rst)
	s_req_raw <= 0;
else if(send_ram_rab_reg=='d680 || (vsout_reg & !vsout))
	s_req_raw <= 1;
else if(s_ack_raw)
	s_req_raw <= 0;

reg	s_req_mask;
always @ (posedge clk or negedge rst)
if(!rst)
	s_req_mask <= 0;
else if(send_ram_rab_reg=='d100 || (vsout_reg & !vsout))
	s_req_mask <= 1;
else if(s_ack_mask)
	s_req_mask <= 0;
	
assign 	pixel = pixel_out;

always @ (posedge clk) begin
	pixel_out <= (send_ram_rdb_mask=='d0) ? send_ram_rdb_raw:send_ram_rdb_mask;//&send_ram_rdb_mask;
	end
endmodule