i2c_altera.map.eqn

filter,很不错,大家可以看以下

--BB1_address_reg_a[1] is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|address_reg_a[1]
--operation mode is normal

BB1_address_reg_a[1]_lut_out = M1_r_ram_rab[13];
BB1_address_reg_a[1] = DFFEAS(BB1_address_reg_a[1]_lut_out, PCLK, VCC, , , , , , );


--BB1_ram_block1a0 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
BB1_ram_block1a0_PORT_A_address = BUS(M1_r_ram_rab[0], M1_r_ram_rab[1], M1_r_ram_rab[2], M1_r_ram_rab[3], M1_r_ram_rab[4], M1_r_ram_rab[5], M1_r_ram_rab[6], M1_r_ram_rab[7], M1_r_ram_rab[8], M1_r_ram_rab[9], M1_r_ram_rab[10], M1_r_ram_rab[11]);
BB1_ram_block1a0_PORT_A_address_reg = DFFE(BB1_ram_block1a0_PORT_A_address, BB1_ram_block1a0_clock_0, , , BB1_ram_block1a0_clock_enable_0);
BB1_ram_block1a0_clock_0 = PCLK;
BB1_ram_block1a0_clock_enable_0 = CB1_w_anode25w[2];
BB1_ram_block1a0_PORT_A_data_out = MEMORY(, , BB1_ram_block1a0_PORT_A_address_reg, , , , , , BB1_ram_block1a0_clock_0, , BB1_ram_block1a0_clock_enable_0, , , );
BB1_ram_block1a0 = BB1_ram_block1a0_PORT_A_data_out[0];


--DB1L1 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~44
--operation mode is normal

DB1L1 = BB1_address_reg_a[0] & (BB1_address_reg_a[1]) # !BB1_address_reg_a[0] & (BB1_address_reg_a[1] & BB1_ram_block1a2 # !BB1_address_reg_a[1] & (BB1_ram_block1a0));


--BB1_ram_block1a3 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a3
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
BB1_ram_block1a3_PORT_A_address = BUS(M1_r_ram_rab[0], M1_r_ram_rab[1], M1_r_ram_rab[2], M1_r_ram_rab[3], M1_r_ram_rab[4], M1_r_ram_rab[5], M1_r_ram_rab[6], M1_r_ram_rab[7], M1_r_ram_rab[8], M1_r_ram_rab[9], M1_r_ram_rab[10], M1_r_ram_rab[11]);
BB1_ram_block1a3_PORT_A_address_reg = DFFE(BB1_ram_block1a3_PORT_A_address, BB1_ram_block1a3_clock_0, , , BB1_ram_block1a3_clock_enable_0);
BB1_ram_block1a3_clock_0 = PCLK;
BB1_ram_block1a3_clock_enable_0 = CB1L5;
BB1_ram_block1a3_PORT_A_data_out = MEMORY(, , BB1_ram_block1a3_PORT_A_address_reg, , , , , , BB1_ram_block1a3_clock_0, , BB1_ram_block1a3_clock_enable_0, , , );
BB1_ram_block1a3 = BB1_ram_block1a3_PORT_A_data_out[0];


--DB1L2 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~45
--operation mode is normal

DB1L2 = BB1_address_reg_a[0] & (DB1L1 & (BB1_ram_block1a3) # !DB1L1 & BB1_ram_block1a1) # !BB1_address_reg_a[0] & (DB1L1);


--M1_qfv_dly1 is add_mask:inst22|qfv_dly1
--operation mode is normal

M1_qfv_dly1_lut_out = M1_qfv_dly;
M1_qfv_dly1 = DFFEAS(M1_qfv_dly1_lut_out, PCLK, VCC, , , , , , );


--M1_byte_cnt[1] is add_mask:inst22|byte_cnt[1]
--operation mode is normal

M1_byte_cnt[1]_lut_out = M1_qfv_dly & (M1_byte_cnt[1] $ M1_byte_cnt[0]);
M1_byte_cnt[1] = DFFEAS(M1_byte_cnt[1]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_byte_cnt[0] is add_mask:inst22|byte_cnt[0]
--operation mode is normal

M1_byte_cnt[0]_lut_out = !M1_byte_cnt[0] & (M1_qfv_dly);
M1_byte_cnt[0] = DFFEAS(M1_byte_cnt[0]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1L31 is add_mask:inst22|always7~0
--operation mode is normal

M1L31 = M1_qfv_dly1 & (!M1_byte_cnt[1] & !M1_byte_cnt[0]);


--M1_data4byte_pre[15] is add_mask:inst22|data4byte_pre[15]
--operation mode is normal

M1_data4byte_pre[15]_lut_out = M1_qd_dly[7];
M1_data4byte_pre[15] = DFFEAS(M1_data4byte_pre[15]_lut_out, PCLK, L1_rst_cnt[23], , M1L751, , , , );


--M1_data4byte_pre[7] is add_mask:inst22|data4byte_pre[7]
--operation mode is normal

M1_data4byte_pre[7]_lut_out = M1_qd_dly[7];
M1_data4byte_pre[7] = DFFEAS(M1_data4byte_pre[7]_lut_out, PCLK, L1_rst_cnt[23], , M1L851, , , , );


--M1_data4byte_pre[31] is add_mask:inst22|data4byte_pre[31]
--operation mode is normal

M1_data4byte_pre[31]_lut_out = M1_qd_dly[7];
M1_data4byte_pre[31] = DFFEAS(M1_data4byte_pre[31]_lut_out, PCLK, L1_rst_cnt[23], , M1L11, , , , );


--M1_qd_dly[7] is add_mask:inst22|qd_dly[7]
--operation mode is normal

M1_qd_dly[7]_lut_out = J1_qfv_even & J1_qd_dly[7] # !J1_qfv_even & (J1_qfv_odd & J1_qd_dly[7] # !J1_qfv_odd & (J1_qd_dly1[7]));
M1_qd_dly[7] = DFFEAS(M1_qd_dly[7]_lut_out, PCLK, VCC, , , , , , );


--GB1_safe_q[0] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|safe_q[0]
--operation mode is arithmetic

GB1_safe_q[0]_lut_out = !GB1_safe_q[0];
GB1_safe_q[0] = DFFEAS(GB1_safe_q[0]_lut_out, PCLK, VCC, , , ~GND, , , GB1_modulus_trigger);

--GB1L3 is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|counter_cella0~COUT
--operation mode is arithmetic

GB1L3 = CARRY(GB1_safe_q[0]);


--GB1_safe_q[1] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|safe_q[1]
--operation mode is arithmetic

GB1_safe_q[1]_carry_eqn = GB1L3;
GB1_safe_q[1]_lut_out = GB1_safe_q[1] $ (GB1_safe_q[1]_carry_eqn);
GB1_safe_q[1] = DFFEAS(GB1_safe_q[1]_lut_out, PCLK, VCC, , , ~GND, , , GB1_modulus_trigger);

--GB1L5 is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|cntr_0fc:cntr1|counter_cella1~COUT
--operation mode is arithmetic

GB1L5 = CARRY(!GB1L3 # !GB1_safe_q[1]);


--M1_qfv_dly4 is add_mask:inst22|qfv_dly4
--operation mode is normal

M1_qfv_dly4_lut_out = M1_qfv_dly3;
M1_qfv_dly4 = DFFEAS(M1_qfv_dly4_lut_out, PCLK, VCC, , , , , , );


--L1_rst_cnt[22] is reset_gen:inst21|rst_cnt[22]
--operation mode is arithmetic

L1_rst_cnt[22]_carry_eqn = L1L54;
L1_rst_cnt[22]_lut_out = L1_rst_cnt[22] $ (!L1_rst_cnt[22]_carry_eqn);
L1_rst_cnt[22] = DFFEAS(L1_rst_cnt[22]_lut_out, PCLK, RST, , !L1_rst_cnt[23], , , , );

--L1L74 is reset_gen:inst21|rst_cnt[22]~199
--operation mode is arithmetic

L1L74 = CARRY(L1_rst_cnt[22] & (!L1L54));


--M1_data4byte_pre[14] is add_mask:inst22|data4byte_pre[14]
--operation mode is normal

M1_data4byte_pre[14]_lut_out = M1_qd_dly[6];
M1_data4byte_pre[14] = DFFEAS(M1_data4byte_pre[14]_lut_out, PCLK, L1_rst_cnt[23], , M1L751, , , , );


--M1_data4byte_pre[22] is add_mask:inst22|data4byte_pre[22]
--operation mode is normal

M1_data4byte_pre[22]_lut_out = M1_qd_dly[6];
M1_data4byte_pre[22] = DFFEAS(M1_data4byte_pre[22]_lut_out, PCLK, L1_rst_cnt[23], , M1L651, , , , );


--M1_data4byte_pre[6] is add_mask:inst22|data4byte_pre[6]
--operation mode is normal

M1_data4byte_pre[6]_lut_out = M1_qd_dly[6];
M1_data4byte_pre[6] = DFFEAS(M1_data4byte_pre[6]_lut_out, PCLK, L1_rst_cnt[23], , M1L851, , , , );


--M1_data4byte_pre[30] is add_mask:inst22|data4byte_pre[30]
--operation mode is normal

M1_data4byte_pre[30]_lut_out = M1_qd_dly[6];
M1_data4byte_pre[30] = DFFEAS(M1_data4byte_pre[30]_lut_out, PCLK, L1_rst_cnt[23], , M1L11, , , , );


--M1_qd_dly[6] is add_mask:inst22|qd_dly[6]
--operation mode is normal

M1_qd_dly[6]_lut_out = J1_qfv_even & J1_qd_dly[6] # !J1_qfv_even & (J1_qfv_odd & J1_qd_dly[6] # !J1_qfv_odd & (J1_qd_dly1[6]));
M1_qd_dly[6] = DFFEAS(M1_qd_dly[6]_lut_out, PCLK, VCC, , , , , , );


--M1_data4byte_pre[21] is add_mask:inst22|data4byte_pre[21]
--operation mode is normal

M1_data4byte_pre[21]_lut_out = M1_qd_dly[5];
M1_data4byte_pre[21] = DFFEAS(M1_data4byte_pre[21]_lut_out, PCLK, L1_rst_cnt[23], , M1L651, , , , );


--M1_data4byte_pre[13] is add_mask:inst22|data4byte_pre[13]
--operation mode is normal

M1_data4byte_pre[13]_lut_out = M1_qd_dly[5];
M1_data4byte_pre[13] = DFFEAS(M1_data4byte_pre[13]_lut_out, PCLK, L1_rst_cnt[23], , M1L751, , , , );


--M1_data4byte_pre[5] is add_mask:inst22|data4byte_pre[5]
--operation mode is normal

M1_data4byte_pre[5]_lut_out = M1_qd_dly[5];
M1_data4byte_pre[5] = DFFEAS(M1_data4byte_pre[5]_lut_out, PCLK, L1_rst_cnt[23], , M1L851, , , , );


--M1_data4byte_pre[29] is add_mask:inst22|data4byte_pre[29]
--operation mode is normal

M1_data4byte_pre[29]_lut_out = M1_qd_dly[5];
M1_data4byte_pre[29] = DFFEAS(M1_data4byte_pre[29]_lut_out, PCLK, L1_rst_cnt[23], , M1L11, , , , );


--M1_qd_dly[5] is add_mask:inst22|qd_dly[5]
--operation mode is normal

M1_qd_dly[5]_lut_out = J1_qfv_even & J1_qd_dly[5] # !J1_qfv_even & (J1_qfv_odd & J1_qd_dly[5] # !J1_qfv_odd & (J1_qd_dly1[5]));
M1_qd_dly[5] = DFFEAS(M1_qd_dly[5]_lut_out, PCLK, VCC, , , , , , );


--M1_data4byte_pre[12] is add_mask:inst22|data4byte_pre[12]
--operation mode is normal

M1_data4byte_pre[12]_lut_out = M1_qd_dly[4];
M1_data4byte_pre[12] = DFFEAS(M1_data4byte_pre[12]_lut_out, PCLK, L1_rst_cnt[23], , M1L751, , , , );


--M1_data4byte_pre[20] is add_mask:inst22|data4byte_pre[20]
--operation mode is normal

M1_data4byte_pre[20]_lut_out = M1_qd_dly[4];
M1_data4byte_pre[20] = DFFEAS(M1_data4byte_pre[20]_lut_out, PCLK, L1_rst_cnt[23], , M1L651, , , , );


--M1_data4byte_pre[4] is add_mask:inst22|data4byte_pre[4]
--operation mode is normal

M1_data4byte_pre[4]_lut_out = M1_qd_dly[4];
M1_data4byte_pre[4] = DFFEAS(M1_data4byte_pre[4]_lut_out, PCLK, L1_rst_cnt[23], , M1L851, , , , );


--M1_data4byte_pre[28] is add_mask:inst22|data4byte_pre[28]
--operation mode is normal

M1_data4byte_pre[28]_lut_out = M1_qd_dly[4];
M1_data4byte_pre[28] = DFFEAS(M1_data4byte_pre[28]_lut_out, PCLK, L1_rst_cnt[23], , M1L11, , , , );


--M1_qd_dly[4] is add_mask:inst22|qd_dly[4]
--operation mode is normal

M1_qd_dly[4]_lut_out = J1_qfv_even & J1_qd_dly[4] # !J1_qfv_even & (J1_qfv_odd & J1_qd_dly[4] # !J1_qfv_odd & (J1_qd_dly1[4]));
M1_qd_dly[4] = DFFEAS(M1_qd_dly[4]_lut_out, PCLK, VCC, , , , , , );


--M1_data4byte_pre[19] is add_mask:inst22|data4byte_pre[19]
--operation mode is normal

M1_data4byte_pre[19]_lut_out = M1_qd_dly[3];
M1_data4byte_pre[19] = DFFEAS(M1_data4byte_pre[19]_lut_out, PCLK, L1_rst_cnt[23], , M1L651, , , , );


--M1_data4byte_pre[11] is add_mask:inst22|data4byte_pre[11]
--operation mode is normal

M1_data4byte_pre[11]_lut_out = M1_qd_dly[3];
M1_data4byte_pre[11] = DFFEAS(M1_data4byte_pre[11]_lut_out, PCLK, L1_rst_cnt[23], , M1L751, , , , );


--M1_data4byte_pre[3] is add_mask:inst22|data4byte_pre[3]
--operation mode is normal

M1_data4byte_pre[3]_lut_out = M1_qd_dly[3];
M1_data4byte_pre[3] = DFFEAS(M1_data4byte_pre[3]_lut_out, PCLK, L1_rst_cnt[23], , M1L851, , , , );


--M1_data4byte_pre[27] is add_mask:inst22|data4byte_pre[27]
--operation mode is normal

M1_data4byte_pre[27]_lut_out = M1_qd_dly[3];
M1_data4byte_pre[27] = DFFEAS(M1_data4byte_pre[27]_lut_out, PCLK, L1_rst_cnt[23], , M1L11, , , , );


--M1_qd_dly[3] is add_mask:inst22|qd_dly[3]
--operation mode is normal

M1_qd_dly[3]_lut_out = J1_qfv_even & J1_qd_dly[3] # !J1_qfv_even & (J1_qfv_odd & J1_qd_dly[3] # !J1_qfv_odd & (J1_qd_dly1[3]));
M1_qd_dly[3] = DFFEAS(M1_qd_dly[3]_lut_out, PCLK, VCC, , , , , , );


--M1_data4byte_pre[10] is add_mask:inst22|data4byte_pre[10]
--operation mode is normal

M1_data4byte_pre[10]_lut_out = M1_qd_dly[2];
M1_data4byte_pre[10] = DFFEAS(M1_data4byte_pre[10]_lut_out, PCLK, L1_rst_cnt[23], , M1L751, , , , );


--M1_data4byte_pre[18] is add_mask:inst22|data4byte_pre[18]
--operation mode is normal

M1_data4byte_pre[18]_lut_out = M1_qd_dly[2];
M1_data4byte_pre[18] = DFFEAS(M1_data4byte_pre[18]_lut_out, PCLK, L1_rst_cnt[23], , M1L651, , , , );


--M1_data4byte_pre[2] is add_mask:inst22|data4byte_pre[2]
--operation mode is normal

M1_data4byte_pre[2]_lut_out = M1_qd_dly[2];
M1_data4byte_pre[2] = DFFEAS(M1_data4byte_pre[2]_lut_out, PCLK, L1_rst_cnt[23], , M1L851, , , , );


--M1_data4byte_pre[26] is add_mask:inst22|data4byte_pre[26]
--operation mode is normal

M1_data4byte_pre[26]_lut_out = M1_qd_dly[2];
M1_data4byte_pre[26] = DFFEAS(M1_data4byte_pre[26]_lut_out, PCLK, L1_rst_cnt[23], , M1L11, , , , );


--M1_qd_dly[2] is add_mask:inst22|qd_dly[2]
--operation mode is normal

M1_qd_dly[2]_lut_out = J1_qfv_even & J1_qd_dly[2] # !J1_qfv_even & (J1_qfv_odd & J1_qd_dly[2] # !J1_qfv_odd & (J1_qd_dly1[2]));
M1_qd_dly[2] = DFFEAS(M1_qd_dly[2]_lut_out, PCLK, VCC, , , , , , );


--M1_data4byte_pre[17] is add_mask:inst22|data4byte_pre[17]
--operation mode is normal

M1_data4byte_pre[17]_lut_out = M1_qd_dly[1];
M1_data4byte_pre[17] = DFFEAS(M1_data4byte_pre[17]_lut_out, PCLK, L1_rst_cnt[23], , M1L651, , , , );


--M1_data4byte_pre[9] is add_mask:inst22|data4byte_pre[9]
--operation mode is normal

M1_data4byte_pre[9]_lut_out = M1_qd_dly[1];
M1_data4byte_pre[9] = DFFEAS(M1_data4byte_pre[9]_lut_out, PCLK, L1_rst_cnt[23], , M1L751, , , , );


--M1_data4byte_pre[1] is add_mask:inst22|data4byte_pre[1]
--operation mode is normal

M1_data4byte_pre[1]_lut_out = M1_qd_dly[1];