i2c_altera.map.eqn

filter,很不错,大家可以看以下

M1_data4byte[28]_lut_out = M1_data4byte_pre[28] # M1_add_mask_ena & DB1L2;
M1_data4byte[28] = DFFEAS(M1_data4byte[28]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L111 is add_mask:inst22|qd_out~206
--operation mode is normal

M1L111 = M1_byte_cnt_out[0] & (M1L011 & (M1_data4byte[28]) # !M1L011 & M1_data4byte[12]) # !M1_byte_cnt_out[0] & (M1L011);


--FB1_q_b[3] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 8, Port B Logical Depth: 3, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
FB1_q_b[3]_PORT_A_data_in = M1_qd_dly[4];
FB1_q_b[3]_PORT_A_data_in_reg = DFFE(FB1_q_b[3]_PORT_A_data_in, FB1_q_b[3]_clock_0, , , );
FB1_q_b[3]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[3]_PORT_A_address_reg = DFFE(FB1_q_b[3]_PORT_A_address, FB1_q_b[3]_clock_0, , , );
FB1_q_b[3]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[3]_PORT_B_address_reg = DFFE(FB1_q_b[3]_PORT_B_address, FB1_q_b[3]_clock_0, , , );
FB1_q_b[3]_PORT_A_write_enable = VCC;
FB1_q_b[3]_PORT_A_write_enable_reg = DFFE(FB1_q_b[3]_PORT_A_write_enable, FB1_q_b[3]_clock_0, , , );
FB1_q_b[3]_PORT_B_read_enable = VCC;
FB1_q_b[3]_PORT_B_read_enable_reg = DFFE(FB1_q_b[3]_PORT_B_read_enable, FB1_q_b[3]_clock_0, , , );
FB1_q_b[3]_clock_0 = PCLK;
FB1_q_b[3]_PORT_B_data_out = MEMORY(FB1_q_b[3]_PORT_A_data_in_reg, , FB1_q_b[3]_PORT_A_address_reg, FB1_q_b[3]_PORT_B_address_reg, FB1_q_b[3]_PORT_A_write_enable_reg, FB1_q_b[3]_PORT_B_read_enable_reg, , , FB1_q_b[3]_clock_0, , , , , );
FB1_q_b[3]_PORT_B_data_out_reg = DFFE(FB1_q_b[3]_PORT_B_data_out, FB1_q_b[3]_clock_0, , , );
FB1_q_b[3] = FB1_q_b[3]_PORT_B_data_out_reg[0];


--M1_data4byte[19] is add_mask:inst22|data4byte[19]
--operation mode is normal

M1_data4byte[19]_lut_out = M1_data4byte_pre[19] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[19] = DFFEAS(M1_data4byte[19]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[11] is add_mask:inst22|data4byte[11]
--operation mode is normal

M1_data4byte[11]_lut_out = M1_data4byte_pre[11] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[11] = DFFEAS(M1_data4byte[11]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[3] is add_mask:inst22|data4byte[3]
--operation mode is normal

M1_data4byte[3]_lut_out = M1_data4byte_pre[3] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[3] = DFFEAS(M1_data4byte[3]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L211 is add_mask:inst22|qd_out~208
--operation mode is normal

M1L211 = M1_byte_cnt_out[1] & (M1_byte_cnt_out[0]) # !M1_byte_cnt_out[1] & (M1_byte_cnt_out[0] & M1_data4byte[11] # !M1_byte_cnt_out[0] & (M1_data4byte[3]));


--M1_data4byte[27] is add_mask:inst22|data4byte[27]
--operation mode is normal

M1_data4byte[27]_lut_out = M1_data4byte_pre[27] # M1_add_mask_ena & DB1L2;
M1_data4byte[27] = DFFEAS(M1_data4byte[27]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L311 is add_mask:inst22|qd_out~209
--operation mode is normal

M1L311 = M1_byte_cnt_out[1] & (M1L211 & (M1_data4byte[27]) # !M1L211 & M1_data4byte[19]) # !M1_byte_cnt_out[1] & (M1L211);


--FB1_q_b[4] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 8, Port B Logical Depth: 3, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
FB1_q_b[4]_PORT_A_data_in = M1_qd_dly[3];
FB1_q_b[4]_PORT_A_data_in_reg = DFFE(FB1_q_b[4]_PORT_A_data_in, FB1_q_b[4]_clock_0, , , );
FB1_q_b[4]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[4]_PORT_A_address_reg = DFFE(FB1_q_b[4]_PORT_A_address, FB1_q_b[4]_clock_0, , , );
FB1_q_b[4]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[4]_PORT_B_address_reg = DFFE(FB1_q_b[4]_PORT_B_address, FB1_q_b[4]_clock_0, , , );
FB1_q_b[4]_PORT_A_write_enable = VCC;
FB1_q_b[4]_PORT_A_write_enable_reg = DFFE(FB1_q_b[4]_PORT_A_write_enable, FB1_q_b[4]_clock_0, , , );
FB1_q_b[4]_PORT_B_read_enable = VCC;
FB1_q_b[4]_PORT_B_read_enable_reg = DFFE(FB1_q_b[4]_PORT_B_read_enable, FB1_q_b[4]_clock_0, , , );
FB1_q_b[4]_clock_0 = PCLK;
FB1_q_b[4]_PORT_B_data_out = MEMORY(FB1_q_b[4]_PORT_A_data_in_reg, , FB1_q_b[4]_PORT_A_address_reg, FB1_q_b[4]_PORT_B_address_reg, FB1_q_b[4]_PORT_A_write_enable_reg, FB1_q_b[4]_PORT_B_read_enable_reg, , , FB1_q_b[4]_clock_0, , , , , );
FB1_q_b[4]_PORT_B_data_out_reg = DFFE(FB1_q_b[4]_PORT_B_data_out, FB1_q_b[4]_clock_0, , , );
FB1_q_b[4] = FB1_q_b[4]_PORT_B_data_out_reg[0];


--M1_data4byte[10] is add_mask:inst22|data4byte[10]
--operation mode is normal

M1_data4byte[10]_lut_out = M1_data4byte_pre[10] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[10] = DFFEAS(M1_data4byte[10]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[18] is add_mask:inst22|data4byte[18]
--operation mode is normal

M1_data4byte[18]_lut_out = M1_data4byte_pre[18] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[18] = DFFEAS(M1_data4byte[18]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[2] is add_mask:inst22|data4byte[2]
--operation mode is normal

M1_data4byte[2]_lut_out = M1_data4byte_pre[2] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[2] = DFFEAS(M1_data4byte[2]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L411 is add_mask:inst22|qd_out~211
--operation mode is normal

M1L411 = M1_byte_cnt_out[0] & (M1_byte_cnt_out[1]) # !M1_byte_cnt_out[0] & (M1_byte_cnt_out[1] & M1_data4byte[18] # !M1_byte_cnt_out[1] & (M1_data4byte[2]));


--M1_data4byte[26] is add_mask:inst22|data4byte[26]
--operation mode is normal

M1_data4byte[26]_lut_out = M1_data4byte_pre[26] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[26] = DFFEAS(M1_data4byte[26]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L511 is add_mask:inst22|qd_out~212
--operation mode is normal

M1L511 = M1_byte_cnt_out[0] & (M1L411 & (M1_data4byte[26]) # !M1L411 & M1_data4byte[10]) # !M1_byte_cnt_out[0] & (M1L411);


--FB1_q_b[5] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 8, Port B Logical Depth: 3, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
FB1_q_b[5]_PORT_A_data_in = M1_qd_dly[2];
FB1_q_b[5]_PORT_A_data_in_reg = DFFE(FB1_q_b[5]_PORT_A_data_in, FB1_q_b[5]_clock_0, , , );
FB1_q_b[5]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[5]_PORT_A_address_reg = DFFE(FB1_q_b[5]_PORT_A_address, FB1_q_b[5]_clock_0, , , );
FB1_q_b[5]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[5]_PORT_B_address_reg = DFFE(FB1_q_b[5]_PORT_B_address, FB1_q_b[5]_clock_0, , , );
FB1_q_b[5]_PORT_A_write_enable = VCC;
FB1_q_b[5]_PORT_A_write_enable_reg = DFFE(FB1_q_b[5]_PORT_A_write_enable, FB1_q_b[5]_clock_0, , , );
FB1_q_b[5]_PORT_B_read_enable = VCC;
FB1_q_b[5]_PORT_B_read_enable_reg = DFFE(FB1_q_b[5]_PORT_B_read_enable, FB1_q_b[5]_clock_0, , , );
FB1_q_b[5]_clock_0 = PCLK;
FB1_q_b[5]_PORT_B_data_out = MEMORY(FB1_q_b[5]_PORT_A_data_in_reg, , FB1_q_b[5]_PORT_A_address_reg, FB1_q_b[5]_PORT_B_address_reg, FB1_q_b[5]_PORT_A_write_enable_reg, FB1_q_b[5]_PORT_B_read_enable_reg, , , FB1_q_b[5]_clock_0, , , , , );
FB1_q_b[5]_PORT_B_data_out_reg = DFFE(FB1_q_b[5]_PORT_B_data_out, FB1_q_b[5]_clock_0, , , );
FB1_q_b[5] = FB1_q_b[5]_PORT_B_data_out_reg[0];


--M1_data4byte[17] is add_mask:inst22|data4byte[17]
--operation mode is normal

M1_data4byte[17]_lut_out = M1_data4byte_pre[17] # M1_add_mask_ena & DB1L2;
M1_data4byte[17] = DFFEAS(M1_data4byte[17]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[9] is add_mask:inst22|data4byte[9]
--operation mode is normal

M1_data4byte[9]_lut_out = M1_data4byte_pre[9] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[9] = DFFEAS(M1_data4byte[9]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[1] is add_mask:inst22|data4byte[1]
--operation mode is normal

M1_data4byte[1]_lut_out = M1_data4byte_pre[1] # M1_add_mask_ena & DB1L2;
M1_data4byte[1] = DFFEAS(M1_data4byte[1]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L611 is add_mask:inst22|qd_out~214
--operation mode is normal

M1L611 = M1_byte_cnt_out[1] & (M1_byte_cnt_out[0]) # !M1_byte_cnt_out[1] & (M1_byte_cnt_out[0] & M1_data4byte[9] # !M1_byte_cnt_out[0] & (M1_data4byte[1]));


--M1_data4byte[25] is add_mask:inst22|data4byte[25]
--operation mode is normal

M1_data4byte[25]_lut_out = M1_data4byte_pre[25] # M1_add_mask_ena & DB1L2;
M1_data4byte[25] = DFFEAS(M1_data4byte[25]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L711 is add_mask:inst22|qd_out~215
--operation mode is normal

M1L711 = M1_byte_cnt_out[1] & (M1L611 & (M1_data4byte[25]) # !M1L611 & M1_data4byte[17]) # !M1_byte_cnt_out[1] & (M1L611);


--FB1_q_b[6] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 8, Port B Logical Depth: 3, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
FB1_q_b[6]_PORT_A_data_in = M1_qd_dly[1];
FB1_q_b[6]_PORT_A_data_in_reg = DFFE(FB1_q_b[6]_PORT_A_data_in, FB1_q_b[6]_clock_0, , , );
FB1_q_b[6]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[6]_PORT_A_address_reg = DFFE(FB1_q_b[6]_PORT_A_address, FB1_q_b[6]_clock_0, , , );
FB1_q_b[6]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[6]_PORT_B_address_reg = DFFE(FB1_q_b[6]_PORT_B_address, FB1_q_b[6]_clock_0, , , );
FB1_q_b[6]_PORT_A_write_enable = VCC;
FB1_q_b[6]_PORT_A_write_enable_reg = DFFE(FB1_q_b[6]_PORT_A_write_enable, FB1_q_b[6]_clock_0, , , );
FB1_q_b[6]_PORT_B_read_enable = VCC;
FB1_q_b[6]_PORT_B_read_enable_reg = DFFE(FB1_q_b[6]_PORT_B_read_enable, FB1_q_b[6]_clock_0, , , );
FB1_q_b[6]_clock_0 = PCLK;
FB1_q_b[6]_PORT_B_data_out = MEMORY(FB1_q_b[6]_PORT_A_data_in_reg, , FB1_q_b[6]_PORT_A_address_reg, FB1_q_b[6]_PORT_B_address_reg, FB1_q_b[6]_PORT_A_write_enable_reg, FB1_q_b[6]_PORT_B_read_enable_reg, , , FB1_q_b[6]_clock_0, , , , , );
FB1_q_b[6]_PORT_B_data_out_reg = DFFE(FB1_q_b[6]_PORT_B_data_out, FB1_q_b[6]_clock_0, , , );
FB1_q_b[6] = FB1_q_b[6]_PORT_B_data_out_reg[0];


--M1_data4byte[8] is add_mask:inst22|data4byte[8]
--operation mode is normal

M1_data4byte[8]_lut_out = M1_data4byte_pre[8] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[8] = DFFEAS(M1_data4byte[8]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[16] is add_mask:inst22|data4byte[16]
--operation mode is normal

M1_data4byte[16]_lut_out = M1_data4byte_pre[16] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[16] = DFFEAS(M1_data4byte[16]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[0] is add_mask:inst22|data4byte[0]
--operation mode is normal

M1_data4byte[0]_lut_out = M1_data4byte_pre[0] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[0] = DFFEAS(M1_data4byte[0]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L811 is add_mask:inst22|qd_out~217
--operation mode is normal

M1L811 = M1_byte_cnt_out[0] & (M1_byte_cnt_out[1]) # !M1_byte_cnt_out[0] & (M1_byte_cnt_out[1] & M1_data4byte[16] # !M1_byte_cnt_out[1] & (M1_data4byte[0]));


--M1_data4byte[24] is add_mask:inst22|data4byte[24]
--operation mode is normal

M1_data4byte[24]_lut_out = M1_data4byte_pre[24] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[24] = DFFEAS(M1_data4byte[24]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L911 is add_mask:inst22|qd_out~218
--operation mode is normal

M1L911 = M1_byte_cnt_out[0] & (M1L811 & (M1_data4byte[24]) # !M1L811 & M1_data4byte[8]) # !M1_byte_cnt_out[0] & (M1L811);


--FB1_q_b[7] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 8, Port B Logical Depth: 3, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
FB1_q_b[7]_PORT_A_data_in = M1_qd_dly[0];
FB1_q_b[7]_PORT_A_data_in_reg = DFFE(FB1_q_b[7]_PORT_A_data_in, FB1_q_b[7]_clock_0, , , );
FB1_q_b[7]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[7]_PORT_A_address_reg = DFFE(FB1_q_b[7]_PORT_A_address, FB1_q_b[7]_clock_0, , , );
FB1_q_b[7]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[7]_PORT_B_address_reg = DFFE(FB1_q_b[7]_PORT_B_address, FB1_q_b[7]_clock_0, , , );
FB1_q_b[7]_PORT_A_write_enable = VCC;
FB1_q_b[7]_PORT_A_write_enable_reg = DFFE(FB1_q_b[7]_PORT_A_write_enable, FB1_q_b[7]_clock_0, , , );
FB1_q_b[7]_PORT_B_read_enable = VCC;
FB1_q_b[7]_PORT_B_read_enable_reg = DFFE(FB1_q_b[7]_PORT_B_read_enable, FB1_q_b[7]_clock_0, , , );
FB1_q_b[7]_clock_0 = PCLK;
FB1_q_b[7]_PORT_B_data_out = MEMORY(FB1_q_b[7]_PORT_A_data_in_reg, , FB1_q_b[7]_PORT_A_address_reg, FB1_q_b[7]_PORT_B_address_reg, FB1_q_b[7]_PORT_A_write_enable_reg, FB1_q_b[7]_PORT_B_read_enable_reg, , , FB1_q_b[7]_clock_0, , , , , );
FB1_q_b[7]_PORT_B_data_out_reg = DFFE(FB1_q_b[7]_PORT_B_data_out, FB1_q_b[7]_clock_0, , , );
FB1_q_b[7] = FB1_q_b[7]_PORT_B_data_out_reg[0];


--F1_dir is Led_run:inst14|dir
--operation mode is normal

F1_dir_lut_out = F1_dir & (F1_led[2] # F1_led[1] # !F1L05) # !F1_dir & F1_led[2] & F1_led[1] & F1L05;
F1_dir = DFFEAS(F1_dir_lut_out, F1_Mega_cnt[23], RST, , , , , , );


--F1_Mega_cnt[23] is Led_run:inst14|Mega_cnt[23]
--operation mode is normal

F1_Mega_cnt[23]_carry_eqn = F1L74;
F1_Mega_cnt[23]_lut_out = F1_Mega_cnt[23] $ (F1_Mega_cnt[23]_carry_eqn);
F1_Mega_cnt[23] = DFFEAS(F1_Mega_cnt[23]_lut_out, SYSCLK, RST, , , , , , );


--M1_data4byte_pre[23] is add_mask:inst22|data4byte_pre[23]
--operation mode is normal

M1_data4byte_pre[23]_lut_out = M1_qd_dly[7];
M1_data4byte_pre[23] = DFFEAS(M1_data4byte_pre[23]_lut_out, PCLK, L1_rst_cnt[23], , M1L651, , , , );


--M1_add_mask_ena is add_mask:inst22|add_mask_ena
--operation mode is normal

M1_add_mask_ena_lut_out = !M1L8 & (M1_row_cnt[5] & (M1L01) # !M1_row_cnt[5] & !M1L9);
M1_add_mask_ena = DFFEAS(M1_add_mask_ena_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--BB1_ram_block1a1 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a1
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
BB1_ram_block1a1_PORT_A_address = BUS(M1_r_ram_rab[0], M1_r_ram_rab[1], M1_r_ram_rab[2], M1_r_ram_rab[3], M1_r_ram_rab[4], M1_r_ram_rab[5], M1_r_ram_rab[6], M1_r_ram_rab[7], M1_r_ram_rab[8], M1_r_ram_rab[9], M1_r_ram_rab[10], M1_r_ram_rab[11]);
BB1_ram_block1a1_PORT_A_address_reg = DFFE(BB1_ram_block1a1_PORT_A_address, BB1_ram_block1a1_clock_0, , , BB1_ram_block1a1_clock_enable_0);
BB1_ram_block1a1_clock_0 = PCLK;
BB1_ram_block1a1_clock_enable_0 = CB1L3;
BB1_ram_block1a1_PORT_A_data_out = MEMORY(, , BB1_ram_block1a1_PORT_A_address_reg, , , , , , BB1_ram_block1a1_clock_0, , BB1_ram_block1a1_clock_enable_0, , , );
BB1_ram_block1a1 = BB1_ram_block1a1_PORT_A_data_out[0];


--BB1_address_reg_a[0] is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|address_reg_a[0]
--operation mode is normal

BB1_address_reg_a[0]_lut_out = M1_r_ram_rab[12];
BB1_address_reg_a[0] = DFFEAS(BB1_address_reg_a[0]_lut_out, PCLK, VCC, , , , , , );


--BB1_ram_block1a2 is add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a2
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
BB1_ram_block1a2_PORT_A_address = BUS(M1_r_ram_rab[0], M1_r_ram_rab[1], M1_r_ram_rab[2], M1_r_ram_rab[3], M1_r_ram_rab[4], M1_r_ram_rab[5], M1_r_ram_rab[6], M1_r_ram_rab[7], M1_r_ram_rab[8], M1_r_ram_rab[9], M1_r_ram_rab[10], M1_r_ram_rab[11]);
BB1_ram_block1a2_PORT_A_address_reg = DFFE(BB1_ram_block1a2_PORT_A_address, BB1_ram_block1a2_clock_0, , , BB1_ram_block1a2_clock_enable_0);
BB1_ram_block1a2_clock_0 = PCLK;
BB1_ram_block1a2_clock_enable_0 = CB1L4;
BB1_ram_block1a2_PORT_A_data_out = MEMORY(, , BB1_ram_block1a2_PORT_A_address_reg, , , , , , BB1_ram_block1a2_clock_0, , BB1_ram_block1a2_clock_enable_0, , , );
BB1_ram_block1a2 = BB1_ram_block1a2_PORT_A_data_out[0];