i2c_altera.map.eqn

filter,很不错,大家可以看以下

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--M1_qd_out[7] is add_mask:inst22|qd_out[7]
--operation mode is normal

M1_qd_out[7]_lut_out = M1_qfv_dly5 & M1L501 # !M1_qfv_dly5 & (FB1_q_b[0]);
M1_qd_out[7] = DFFEAS(M1_qd_out[7]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_qd_out[6] is add_mask:inst22|qd_out[6]
--operation mode is normal

M1_qd_out[6]_lut_out = M1_qfv_dly5 & M1L701 # !M1_qfv_dly5 & (FB1_q_b[1]);
M1_qd_out[6] = DFFEAS(M1_qd_out[6]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_qd_out[5] is add_mask:inst22|qd_out[5]
--operation mode is normal

M1_qd_out[5]_lut_out = M1_qfv_dly5 & M1L901 # !M1_qfv_dly5 & (FB1_q_b[2]);
M1_qd_out[5] = DFFEAS(M1_qd_out[5]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_qd_out[4] is add_mask:inst22|qd_out[4]
--operation mode is normal

M1_qd_out[4]_lut_out = M1_qfv_dly5 & M1L111 # !M1_qfv_dly5 & (FB1_q_b[3]);
M1_qd_out[4] = DFFEAS(M1_qd_out[4]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_qd_out[3] is add_mask:inst22|qd_out[3]
--operation mode is normal

M1_qd_out[3]_lut_out = M1_qfv_dly5 & M1L311 # !M1_qfv_dly5 & (FB1_q_b[4]);
M1_qd_out[3] = DFFEAS(M1_qd_out[3]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_qd_out[2] is add_mask:inst22|qd_out[2]
--operation mode is normal

M1_qd_out[2]_lut_out = M1_qfv_dly5 & M1L511 # !M1_qfv_dly5 & (FB1_q_b[5]);
M1_qd_out[2] = DFFEAS(M1_qd_out[2]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_qd_out[1] is add_mask:inst22|qd_out[1]
--operation mode is normal

M1_qd_out[1]_lut_out = M1_qfv_dly5 & M1L711 # !M1_qfv_dly5 & (FB1_q_b[6]);
M1_qd_out[1] = DFFEAS(M1_qd_out[1]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_qd_out[0] is add_mask:inst22|qd_out[0]
--operation mode is normal

M1_qd_out[0]_lut_out = M1_qfv_dly5 & M1L911 # !M1_qfv_dly5 & (FB1_q_b[7]);
M1_qd_out[0] = DFFEAS(M1_qd_out[0]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--F1_led[3] is Led_run:inst14|led[3]
--operation mode is normal

F1_led[3]_lut_out = F1_led[2] & (!F1_dir);
F1_led[3] = DFFEAS(F1_led[3]_lut_out, F1_Mega_cnt[23], RST, , , , , , );


--F1_led[2] is Led_run:inst14|led[2]
--operation mode is normal

F1_led[2]_lut_out = F1_dir & F1_led[3] # !F1_dir & (!F1_led[1]);
F1_led[2] = DFFEAS(F1_led[2]_lut_out, F1_Mega_cnt[23], RST, , , , , , );


--F1_led[1] is Led_run:inst14|led[1]
--operation mode is normal

F1_led[1]_lut_out = F1_dir & !F1_led[2] # !F1_dir & (!F1_led[0]);
F1_led[1] = DFFEAS(F1_led[1]_lut_out, F1_Mega_cnt[23], RST, , , , , , );


--F1_led[0] is Led_run:inst14|led[0]
--operation mode is normal

F1_led[0]_lut_out = F1_dir & (!F1_led[1]);
F1_led[0] = DFFEAS(F1_led[0]_lut_out, F1_Mega_cnt[23], RST, , , , , , );


--M1_data4byte[23] is add_mask:inst22|data4byte[23]
--operation mode is normal

M1_data4byte[23]_lut_out = M1_data4byte_pre[23] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[23] = DFFEAS(M1_data4byte[23]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_byte_cnt_out[1] is add_mask:inst22|byte_cnt_out[1]
--operation mode is normal

M1_byte_cnt_out[1]_lut_out = M1_qfv_dly5 & (M1_byte_cnt_out[1] $ M1_byte_cnt_out[0]);
M1_byte_cnt_out[1] = DFFEAS(M1_byte_cnt_out[1]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_data4byte[15] is add_mask:inst22|data4byte[15]
--operation mode is normal

M1_data4byte[15]_lut_out = M1_data4byte_pre[15] # M1_add_mask_ena & DB1L2;
M1_data4byte[15] = DFFEAS(M1_data4byte[15]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_byte_cnt_out[0] is add_mask:inst22|byte_cnt_out[0]
--operation mode is normal

M1_byte_cnt_out[0]_lut_out = !M1_byte_cnt_out[0] & (M1_qfv_dly5);
M1_byte_cnt_out[0] = DFFEAS(M1_byte_cnt_out[0]_lut_out, PCLK, L1_rst_cnt[23], , , , , , );


--M1_data4byte[7] is add_mask:inst22|data4byte[7]
--operation mode is normal

M1_data4byte[7]_lut_out = M1_data4byte_pre[7] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[7] = DFFEAS(M1_data4byte[7]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L401 is add_mask:inst22|qd_out~196
--operation mode is normal

M1L401 = M1_byte_cnt_out[1] & (M1_byte_cnt_out[0]) # !M1_byte_cnt_out[1] & (M1_byte_cnt_out[0] & M1_data4byte[15] # !M1_byte_cnt_out[0] & (M1_data4byte[7]));


--M1_data4byte[31] is add_mask:inst22|data4byte[31]
--operation mode is normal

M1_data4byte[31]_lut_out = M1_data4byte_pre[31] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[31] = DFFEAS(M1_data4byte[31]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L501 is add_mask:inst22|qd_out~197
--operation mode is normal

M1L501 = M1_byte_cnt_out[1] & (M1L401 & (M1_data4byte[31]) # !M1L401 & M1_data4byte[23]) # !M1_byte_cnt_out[1] & (M1L401);


--FB1_q_b[0] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 8, Port B Logical Depth: 3, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
FB1_q_b[0]_PORT_A_data_in = M1_qd_dly[7];
FB1_q_b[0]_PORT_A_data_in_reg = DFFE(FB1_q_b[0]_PORT_A_data_in, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_A_address_reg = DFFE(FB1_q_b[0]_PORT_A_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[0]_PORT_B_address_reg = DFFE(FB1_q_b[0]_PORT_B_address, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_A_write_enable = VCC;
FB1_q_b[0]_PORT_A_write_enable_reg = DFFE(FB1_q_b[0]_PORT_A_write_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_PORT_B_read_enable = VCC;
FB1_q_b[0]_PORT_B_read_enable_reg = DFFE(FB1_q_b[0]_PORT_B_read_enable, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0]_clock_0 = PCLK;
FB1_q_b[0]_PORT_B_data_out = MEMORY(FB1_q_b[0]_PORT_A_data_in_reg, , FB1_q_b[0]_PORT_A_address_reg, FB1_q_b[0]_PORT_B_address_reg, FB1_q_b[0]_PORT_A_write_enable_reg, FB1_q_b[0]_PORT_B_read_enable_reg, , , FB1_q_b[0]_clock_0, , , , , );
FB1_q_b[0]_PORT_B_data_out_reg = DFFE(FB1_q_b[0]_PORT_B_data_out, FB1_q_b[0]_clock_0, , , );
FB1_q_b[0] = FB1_q_b[0]_PORT_B_data_out_reg[0];


--M1_qfv_dly5 is add_mask:inst22|qfv_dly5
--operation mode is normal

M1_qfv_dly5_lut_out = M1_qfv_dly4;
M1_qfv_dly5 = DFFEAS(M1_qfv_dly5_lut_out, PCLK, VCC, , , , , , );


--L1_rst_cnt[23] is reset_gen:inst21|rst_cnt[23]
--operation mode is normal

L1_rst_cnt[23]_carry_eqn = L1L74;
L1_rst_cnt[23]_lut_out = L1_rst_cnt[23] $ (L1_rst_cnt[23]_carry_eqn);
L1_rst_cnt[23] = DFFEAS(L1_rst_cnt[23]_lut_out, PCLK, RST, , !L1_rst_cnt[23], , , , );


--M1_data4byte[14] is add_mask:inst22|data4byte[14]
--operation mode is normal

M1_data4byte[14]_lut_out = M1_data4byte_pre[14] # M1_add_mask_ena & DB1L2;
M1_data4byte[14] = DFFEAS(M1_data4byte[14]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[22] is add_mask:inst22|data4byte[22]
--operation mode is normal

M1_data4byte[22]_lut_out = M1_data4byte_pre[22] # M1_add_mask_ena & DB1L2;
M1_data4byte[22] = DFFEAS(M1_data4byte[22]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[6] is add_mask:inst22|data4byte[6]
--operation mode is normal

M1_data4byte[6]_lut_out = M1_data4byte_pre[6] # M1_add_mask_ena & DB1L2;
M1_data4byte[6] = DFFEAS(M1_data4byte[6]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L601 is add_mask:inst22|qd_out~199
--operation mode is normal

M1L601 = M1_byte_cnt_out[0] & (M1_byte_cnt_out[1]) # !M1_byte_cnt_out[0] & (M1_byte_cnt_out[1] & M1_data4byte[22] # !M1_byte_cnt_out[1] & (M1_data4byte[6]));


--M1_data4byte[30] is add_mask:inst22|data4byte[30]
--operation mode is normal

M1_data4byte[30]_lut_out = M1_data4byte_pre[30] # M1_add_mask_ena & DB1L2;
M1_data4byte[30] = DFFEAS(M1_data4byte[30]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L701 is add_mask:inst22|qd_out~200
--operation mode is normal

M1L701 = M1_byte_cnt_out[0] & (M1L601 & (M1_data4byte[30]) # !M1L601 & M1_data4byte[14]) # !M1_byte_cnt_out[0] & (M1L601);


--FB1_q_b[1] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 8, Port B Logical Depth: 3, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
FB1_q_b[1]_PORT_A_data_in = M1_qd_dly[6];
FB1_q_b[1]_PORT_A_data_in_reg = DFFE(FB1_q_b[1]_PORT_A_data_in, FB1_q_b[1]_clock_0, , , );
FB1_q_b[1]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[1]_PORT_A_address_reg = DFFE(FB1_q_b[1]_PORT_A_address, FB1_q_b[1]_clock_0, , , );
FB1_q_b[1]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[1]_PORT_B_address_reg = DFFE(FB1_q_b[1]_PORT_B_address, FB1_q_b[1]_clock_0, , , );
FB1_q_b[1]_PORT_A_write_enable = VCC;
FB1_q_b[1]_PORT_A_write_enable_reg = DFFE(FB1_q_b[1]_PORT_A_write_enable, FB1_q_b[1]_clock_0, , , );
FB1_q_b[1]_PORT_B_read_enable = VCC;
FB1_q_b[1]_PORT_B_read_enable_reg = DFFE(FB1_q_b[1]_PORT_B_read_enable, FB1_q_b[1]_clock_0, , , );
FB1_q_b[1]_clock_0 = PCLK;
FB1_q_b[1]_PORT_B_data_out = MEMORY(FB1_q_b[1]_PORT_A_data_in_reg, , FB1_q_b[1]_PORT_A_address_reg, FB1_q_b[1]_PORT_B_address_reg, FB1_q_b[1]_PORT_A_write_enable_reg, FB1_q_b[1]_PORT_B_read_enable_reg, , , FB1_q_b[1]_clock_0, , , , , );
FB1_q_b[1]_PORT_B_data_out_reg = DFFE(FB1_q_b[1]_PORT_B_data_out, FB1_q_b[1]_clock_0, , , );
FB1_q_b[1] = FB1_q_b[1]_PORT_B_data_out_reg[0];


--M1_data4byte[21] is add_mask:inst22|data4byte[21]
--operation mode is normal

M1_data4byte[21]_lut_out = M1_data4byte_pre[21] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[21] = DFFEAS(M1_data4byte[21]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[13] is add_mask:inst22|data4byte[13]
--operation mode is normal

M1_data4byte[13]_lut_out = M1_data4byte_pre[13] # M1_add_mask_ena & DB1L2;
M1_data4byte[13] = DFFEAS(M1_data4byte[13]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[5] is add_mask:inst22|data4byte[5]
--operation mode is normal

M1_data4byte[5]_lut_out = M1_data4byte_pre[5] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[5] = DFFEAS(M1_data4byte[5]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L801 is add_mask:inst22|qd_out~202
--operation mode is normal

M1L801 = M1_byte_cnt_out[1] & (M1_byte_cnt_out[0]) # !M1_byte_cnt_out[1] & (M1_byte_cnt_out[0] & M1_data4byte[13] # !M1_byte_cnt_out[0] & (M1_data4byte[5]));


--M1_data4byte[29] is add_mask:inst22|data4byte[29]
--operation mode is normal

M1_data4byte[29]_lut_out = M1_data4byte_pre[29] & (!DB1L2 # !M1_add_mask_ena);
M1_data4byte[29] = DFFEAS(M1_data4byte[29]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L901 is add_mask:inst22|qd_out~203
--operation mode is normal

M1L901 = M1_byte_cnt_out[1] & (M1L801 & (M1_data4byte[29]) # !M1L801 & M1_data4byte[21]) # !M1_byte_cnt_out[1] & (M1L801);


--FB1_q_b[2] is add_mask:inst22|altshift_taps:qd_dly1_rtl_0|shift_taps_1jg:auto_generated|altsyncram_kqu:altsyncram2|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 3, Port A Width: 1, Port B Depth: 3, Port B Width: 1
--Port A Logical Depth: 3, Port A Logical Width: 8, Port B Logical Depth: 3, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Registered
FB1_q_b[2]_PORT_A_data_in = M1_qd_dly[5];
FB1_q_b[2]_PORT_A_data_in_reg = DFFE(FB1_q_b[2]_PORT_A_data_in, FB1_q_b[2]_clock_0, , , );
FB1_q_b[2]_PORT_A_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[2]_PORT_A_address_reg = DFFE(FB1_q_b[2]_PORT_A_address, FB1_q_b[2]_clock_0, , , );
FB1_q_b[2]_PORT_B_address = BUS(GB1_safe_q[0], GB1_safe_q[1]);
FB1_q_b[2]_PORT_B_address_reg = DFFE(FB1_q_b[2]_PORT_B_address, FB1_q_b[2]_clock_0, , , );
FB1_q_b[2]_PORT_A_write_enable = VCC;
FB1_q_b[2]_PORT_A_write_enable_reg = DFFE(FB1_q_b[2]_PORT_A_write_enable, FB1_q_b[2]_clock_0, , , );
FB1_q_b[2]_PORT_B_read_enable = VCC;
FB1_q_b[2]_PORT_B_read_enable_reg = DFFE(FB1_q_b[2]_PORT_B_read_enable, FB1_q_b[2]_clock_0, , , );
FB1_q_b[2]_clock_0 = PCLK;
FB1_q_b[2]_PORT_B_data_out = MEMORY(FB1_q_b[2]_PORT_A_data_in_reg, , FB1_q_b[2]_PORT_A_address_reg, FB1_q_b[2]_PORT_B_address_reg, FB1_q_b[2]_PORT_A_write_enable_reg, FB1_q_b[2]_PORT_B_read_enable_reg, , , FB1_q_b[2]_clock_0, , , , , );
FB1_q_b[2]_PORT_B_data_out_reg = DFFE(FB1_q_b[2]_PORT_B_data_out, FB1_q_b[2]_clock_0, , , );
FB1_q_b[2] = FB1_q_b[2]_PORT_B_data_out_reg[0];


--M1_data4byte[12] is add_mask:inst22|data4byte[12]
--operation mode is normal

M1_data4byte[12]_lut_out = M1_data4byte_pre[12] # M1_add_mask_ena & DB1L2;
M1_data4byte[12] = DFFEAS(M1_data4byte[12]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[20] is add_mask:inst22|data4byte[20]
--operation mode is normal

M1_data4byte[20]_lut_out = M1_data4byte_pre[20] # M1_add_mask_ena & DB1L2;
M1_data4byte[20] = DFFEAS(M1_data4byte[20]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1_data4byte[4] is add_mask:inst22|data4byte[4]
--operation mode is normal

M1_data4byte[4]_lut_out = M1_data4byte_pre[4] # M1_add_mask_ena & DB1L2;
M1_data4byte[4] = DFFEAS(M1_data4byte[4]_lut_out, PCLK, L1_rst_cnt[23], , M1L31, , , , );


--M1L011 is add_mask:inst22|qd_out~205
--operation mode is normal

M1L011 = M1_byte_cnt_out[0] & (M1_byte_cnt_out[1]) # !M1_byte_cnt_out[0] & (M1_byte_cnt_out[1] & M1_data4byte[20] # !M1_byte_cnt_out[1] & (M1_data4byte[4]));


--M1_data4byte[28] is add_mask:inst22|data4byte[28]
--operation mode is normal