sync_gen.v

filter,很不错,大家可以看以下

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/* Title          :	virtual image source                          */
/* Project        :	virtual source                                */
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// File name      :  receiver.v 
// Purpose        :    
// Author<email>  :  [e-mail]
// Created On     :  2003/09/27
// Last update    :	 2003/09/27 
// Platform :     :	 Windows2000 
// Simulators     :	 MaxplussII 10.1 
// Synthesizers   :	 MaxplussII 10.1 
// Targets Device :	 (MAX7000AE)EPM7128AETC100-10 
// Comments       :  -
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module sync_gen(
	rst,					
	qd,
	clk,
	
	odd_even_sig,
	frame_syc,
	
	STATE
	);					
/*** ports ***/
input	rst;
input	[7:0]	qd;
input	clk;

output	odd_even_sig;
output	frame_syc;
output	[2:0]	STATE;
//internal 
reg	[7:0]	qd_dly,qd_dly1,qd_dly2;

always @ (posedge clk) begin	
	qd_dly  <= qd;
	qd_dly1 <= qd_dly;
	qd_dly2 <= qd_dly1;
	end
	
reg	[2:0]	STATE;
always @ (posedge clk or negedge rst)
if(!rst) begin
	STATE <= 0;
	end
else 
	case(STATE)
	3'd0:	if(qd_dly==8'hff)
			STATE <= 3'd1;
		else
			STATE <= 3'd0;
	3'd1:	if(qd_dly==8'h00)
			STATE <= 3'd2;
		else if(qd_dly == 8'hff)
			STATE <= 1'b1;
		else
			STATE <= 3'd0;
	3'd2:	if(qd_dly==8'h00)
			STATE <= 3'd3;
		else
			STATE <= 3'd0;
	3'd3:	if(qd_dly==8'hB6)
			STATE <= 3'd4;
		else if(qd_dly==8'hF1)
			STATE <= 3'd5;
		else
			STATE <= 3'd0;
	3'd4:	STATE <= 1'b0;
	3'd5:	STATE <= 1'b0;
	endcase	

reg	[4:0]	odd_cnt;
always @ (posedge clk or negedge rst)
if(!rst)
	odd_cnt <= 1'b0;
else if(STATE == 3'd4)
	odd_cnt <= odd_cnt + 1'b1;
else if(STATE == 3'd5)
	odd_cnt <= 1'b0;	

reg	[4:0]	even_cnt;
always @ (posedge clk or negedge rst)
if(!rst)
	even_cnt <= 1'b0;
else if(STATE == 3'd5)
	even_cnt <= even_cnt + 1'b1;
else if(STATE == 3'd4)
	even_cnt <= 1'b0;
		
reg	odd_even_sig;
always @ (posedge clk or negedge rst)
if(!rst)
	odd_even_sig <= 1'b0;
else if((STATE == 3'd4)&& (odd_cnt == 3'd5))
	odd_even_sig <= 1'b1;
else if((STATE == 3'd5)&& (even_cnt == 3'd5))
	odd_even_sig <= 1'b0;	

reg	frame_syc;
always @ (posedge clk or negedge rst)
if(!rst)
	frame_syc <= 1'b0;
else if(odd_cnt == 3'd7 && odd_even_sig)
	frame_syc <= 1'b1;
else 
	frame_syc <= 1'b0;	
endmodule