receiver_2.v

filter,很不错,大家可以看以下

module receiver_2(clk,rst,datain,data_out_f);
input clk,rst;
input[7:0] datain;
reg[7:0] datain_1dly,datain_2dly,datain_3dly,datain_4dly,datain_5dly,datain_6dly,datain_7dly;
reg ena,vsync,hsync,hsync_dly,hsync_dly_dly,hsync_dly_dly_dly,hsync_4dly,hsync_5dly,hsync_6dly,hsync_7dly,ena_out;
output[7:0] data_out_f;
reg[7:0] data_out_eight,data_out_f;
reg[8:0] counter;
reg[1:0] state,state_out;
reg[2:0] state_ena;
reg odd_start;
reg[1:0] counter1;
reg[31:0] data1,data2,dataout;
reg[9:0] h_cnt;
reg h_sync,h_sync_dly;
wire data;
reg[13:0] addr;

parameter Idel=2'b00,state1=2'b01,state2=2'b10,
          state3=2'b11;
 
always @ (posedge clk or negedge rst)
   begin
        if(!rst)           
           begin
                state<=Idel;
                vsync<=1'b0;
                hsync<=1'b0;
                odd_start<=1'b0;
                h_sync<=1'b0;
           end
        else
            case(state)
              Idel: begin
                     if(datain==8'hff)
                        state<=state1;
                     else
                        state<=Idel;
                    end
              state1: begin
                       if(datain==8'hff)
                          state<=state1;
                       else if(datain==8'h00)
                          state<=state2;
                       else 
                          state<=Idel;
                      end
              state2: begin
                       if(datain==8'h00)
                          state<=state3;
                       else 
                          state<=Idel;
                      end     
              state3: begin
                       if(datain==8'hc7)
                         begin 
                          state<=Idel;
                          odd_start<=1'b1;
                          vsync<=1'b1;
                          hsync<=1'b1;
                          h_sync<=1'b1;
                         end                  
                       else if(datain==8'h80)
                          begin
                           state<=Idel;              
                           odd_start<=1'b0;
                           vsync<=1'b1;
                           hsync<=1'b1;
                           h_sync<=1'b1;
                          end
                       else if(datain==8'hb8 || datain==8'h70)
                          begin
                           state<=Idel;
                           odd_start<=1'b0;
                           h_sync<=1'b1;
                          end  
                       else if(datain==8'h9d || datain==8'hda)
                          begin
                           state<=Idel;
                           odd_start<=1'b0;
                           hsync<=1'b0;
                           h_sync<=1'b0;
                          end
                       else if(datain==8'h83 || datain==8'h84)
                          begin
                           state<=Idel;
                           odd_start<=1'b0;
                           vsync<=1'b0;
                           hsync<=1'b0;
                           h_sync<=1'b0;
                          end
                       else
                          state<=Idel;
                      end 
              default: state<=4'b0;   
            endcase
   end
always @ (posedge clk)
 begin
  hsync_dly<=hsync;
  hsync_dly_dly<=hsync_dly;
  hsync_dly_dly_dly<=hsync_dly_dly;
  hsync_4dly<=hsync_dly_dly_dly;
  hsync_5dly<=hsync_4dly;
  hsync_6dly<=hsync_5dly;
  hsync_7dly<=hsync_6dly;
 end
  
always @ (posedge clk or negedge rst)
   begin
     if(!rst)
        counter<=9'd0;
     else if(counter==288)
        counter<=9'b0;
     else if(hsync==1 && hsync_dly==0)         
        counter<=counter+9'd1;
     else 
        counter<=counter;
   end

always @ (posedge clk)
  h_sync_dly<=h_sync;

always @ (posedge clk or negedge rst)
   begin
     if(!rst)
		h_cnt<=10'd0;    
     else if(h_cnt==600)
        h_cnt<=10'b0;
     else if(h_sync==1 && h_sync_dly==0)         
        h_cnt<=h_cnt+10'd1;
     else 
        h_cnt<=h_cnt;
   end
  
always @ (posedge clk or negedge rst)
   begin
     if(!rst)
        counter1<=2'b0;
     else
       begin 
         if(hsync==1)
           begin  
             if(counter1==3)
                counter1<=2'b0;
             else
                counter1<=counter1+2'd1;
           end    
         else
           counter1<=2'b0;
       end       
   end
 
always @ (posedge clk or negedge rst)
  begin
    if(!rst)
     begin
      state_ena<=0;
      data1<=0;
      ena<=1'b0;
     end
    else
      case(state_ena)
        0: begin
             if(counter1==0 && vsync==1'b1 && hsync==1'b1)
              begin
               state_ena<=1;                  
               data1[7:0]<=datain;
              end
             else
              begin
               state_ena<=0; 
               data1<=0;
              end
           end
        1: begin 
             if(counter1==1)            
              begin
               state_ena<=2;
               ena<=1'b0;
               data1[15:8]<=datain;
              end     
             else
              begin
               state_ena<=0;
               data1<=0;
               ena<=1'b0;
              end
           end
        2: begin
             if(counter1==2) 
              begin 
               state_ena<=3;
               data1[23:16]<=datain; 
              end
             else
              begin
               state_ena<=0;
               data1<=0;
              end  
           end 
        3: begin
             if(counter1==3)
              begin 
               state_ena<=4;
               data1[31:24]<=datain;
              end
             else
              begin
               state_ena<=0;
               data1<=0;
              end
           end
        4: begin
             if(counter1==0 && hsync==1'b1)
              begin
               state_ena<=1;
               ena<=1'b1;
               data2<=data1;
               data1[7:0]<=datain;
              end
             else
              begin 
               state_ena<=0;
               data1<=0;
              end
           end
      endcase
  end

always @ (posedge clk or negedge rst)  //待扩展//
  begin
    if(!rst)
     begin
      ena_out<=1'b0;   
      dataout<=0;
     end
    else if(ena==1'b1)
      begin
         if(data==1'b0 || counter>=31)
           begin
                dataout<=data2;
            	ena_out<=1'b1;
           end 
          else
           begin
             dataout[31:24]<=8'h80;
			 dataout[23:16]<=8'h10;
			 dataout[15:8]<=8'h80;
			 dataout[7:0]<=8'h10;
             ena_out<=1'b1;
           end 
      end      
    else 
     begin 
      dataout<=dataout;        
      ena_out<=1'b0;
     end
  end

always @ (posedge clk or negedge rst)
 begin 
  if(!rst)
   begin
    state_out<=2'b0; 
    data_out_eight<=8'hxx;
   end
  else if(hsync_dly_dly==1'b1)
  begin
  if(ena_out==1)
   begin 
    state_out<=2'b1;
    data_out_eight<=dataout[7:0];
   end
  else
   case(state_out)
    2'd1: begin
         state_out<=2;
         data_out_eight<=dataout[15:8];
       end
    2'd2: begin
         state_out<=3;
         data_out_eight<=dataout[23:16];
       end
    2'd3: begin
           data_out_eight<=dataout[31:24];
          end
    default: begin
         data_out_eight<=8'hxx;
       end  
   endcase 
  end
  else
    begin 
     data_out_eight<=8'hxx; 
     state_out<=2'b0;
    end       
 end

always @ (posedge clk)
 begin
   datain_1dly<=datain;
   datain_2dly<=datain_1dly;
   datain_3dly<=datain_2dly;
   datain_4dly<=datain_3dly;
   datain_5dly<=datain_4dly;
   datain_6dly<=datain_5dly;
   datain_7dly<=datain_6dly;
 end

always @ (posedge clk or negedge rst)
 begin
 if(!rst)
   data_out_f<=8'hxx;
 else if(hsync_dly_dly_dly==1'b1 && hsync_7dly==1'b1)
   data_out_f<=data_out_eight;
 else 
   data_out_f<=datain_7dly;     
 end

always @ (posedge clk or negedge rst)
 begin
   if(!rst)
     addr<=1'd0;
   else if(counter>=1 && counter<=30)
    begin 
    if(ena==1)
     begin
        if(addr==10799)
            addr<=14'd0;
        else
          addr<=addr+1'b1;
     end  
    else
     addr<=addr;
   end
  else
    addr<=1'b0;  
 end

mask_rom m(.clock(clk),.address(addr),.q(data));

endmodule