receive_pal.v

filter,很不错,大家可以看以下

/*******************************************************************/
/* Title          :	virtual image source                          */
/* Project        :	virtual source                                */
/*******************************************************************/

/*******************************************************************/
// File name      :  receiver.v 
// Purpose        :    
// Author<email>  :  [e-mail]
// Created On     :  2003/09/27
// Last update    :	 2003/09/27 
// Platform :     :	 Windows2000 
// Simulators     :	 MaxplussII 10.1 
// Synthesizers   :	 MaxplussII 10.1 
// Targets Device :	 (MAX7000AE)EPM7128AETC100-10 
// Comments       :  -
/*******************************************************************/

/*******************************************************************/
/*******************************************************************/

/*******************************************************************/
/* Revision History :											   */
/*******************************************************************/
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// Version         : 
// Date            : 
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// Desccription    :   
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// Revision Number : 
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module receiver_pal(
	rst,	
	qd,
	clk,
	qfv,
	odd_even_in,
	
	r_ram_wdb,
	r_ram_wab,
	r_ram_wen,

	r_ram_wdb_test,
		
	r_req,
	r_ack,
	
	start_read
	);					
/*** ports ***/
input	rst;
input	[7:0]	qd;
input	clk,qfv;
input	r_ack;
input	odd_even_in;
output	[7:0]	r_ram_wdb,r_ram_wdb_test;
output	r_req;
output	[10:0]	r_ram_wab;
output	r_ram_wen;
output	start_read;


//internal 

reg	qfv_dly;
reg	[7:0]	qd_dly;
reg	r_ack_dly;
reg	odd_even_dly;
always @ (posedge clk) begin	
	qd_dly  <= qd;
	qfv_dly <= qfv;
	r_ack_dly <= r_ack;
	odd_even_dly <= odd_even_in;
	end

reg	[2:0]	STATE;
always @ (posedge clk or negedge rst)
if(!rst) begin
	STATE <= 2'd3;
	end
else 
	case(STATE)
	2'd3:	if(odd_even_dly)
			STATE <= 1'b0;
			else
			STATE <= 2'd3;
	2'd0:	if(qfv_dly)
			STATE <= 2'd1;
		else
			STATE <= 2'd0;
	2'd1:	if(!qfv_dly)
			STATE <= 2'd2;
		else
			STATE <= 2'd1;
	2'd2:	STATE <= 3'd0;
	endcase	
	
reg	start_read;	
always @ (posedge clk or negedge rst)
if(!rst)
	start_read <= 1'b0;
else if(STATE=='d1)
	start_read <= 1'b1;
	
reg	[9:0]	r_ram_wab_reg;                                                      
always @ (posedge  clk or negedge rst)
if(!rst)
	r_ram_wab_reg <= 1'b0;
else if(qfv_dly && STATE!=2'd3) begin
	if(r_ram_wab_reg == 10'd719)
		r_ram_wab_reg <= 1'b0;
	else
		r_ram_wab_reg <= r_ram_wab_reg + 1'b1;
	end
else
	r_ram_wab_reg <= 0;

reg	r_ram_wab_hbit;
always @ (posedge clk or negedge rst)
if(!rst)
	r_ram_wab_hbit <= 1'b0;
else if(STATE == 2'd2)
	r_ram_wab_hbit <= 1'b0;
else if(r_ram_wab_reg == 10'd719)
	r_ram_wab_hbit <= ~r_ram_wab_hbit;
		
wire	[10:0]	r_ram_wab = {r_ram_wab_hbit,r_ram_wab_reg};

wire	[7:0]	r_ram_wdb = qd_dly;

reg	[7:0]	r_ram_wdb_test;
always @ (posedge clk or negedge rst)
if(!rst)
	r_ram_wdb_test <= 1'b0;
else if(qfv_dly)
	r_ram_wdb_test <= r_ram_wdb_test + 1'b1;
else 
	r_ram_wdb_test <= 1'b0;

reg	r_req;
always @ (posedge clk or negedge rst)
if(!rst)
    r_req<= 1'b0;
else if(r_ram_wab_reg==10'd700 )
    r_req<= 1'b1;
else if(r_ack_dly)
    r_req <= 1'b0;

wire	r_ram_wen = qfv_dly;
endmodule