sender_vga.v

filter,很不错,大家可以看以下

`timescale 1ns / 1ns

module sender_vga(	
	rst,						//main reset
	clk,				     	       //system clock
                
	hsin,
	vsin,
	blankin,
	blank_NTSC,

	pixel_R,
	pixel_G,
	pixel_B,
	        
	send_ram_rdb_raw,
	
	send_ram_rab_raw,
 
	s_req_raw,
	s_ack_raw,
        
	hsout,
	vsout,
	blankout
              );						


/***input and output ***/
input	rst,clk,s_ack_raw;
input	hsin,vsin,blankin;
input	blank_NTSC;

input	[31:0]	send_ram_rdb_raw;

output	[7:0]	pixel_R;
output	[7:0]	pixel_G;
output	[7:0]	pixel_B;
output	[8:0]	send_ram_rab_raw;

output	hsout;
output	vsout;
output	blankout;

output	s_req_raw;

reg	s_req_raw;

reg	[7:0]	pixel_R;
reg	[7:0]	pixel_G;
reg	[7:0]	pixel_B;

reg	hsout_dly;
reg	hsout;
reg	vsout_dly;
reg	vsout;
reg	blankout;
reg	blankout_dly;
reg	blank_ntsc_dly1;
reg	blank_ntsc_dly; 

always @ (posedge clk) begin
	hsout_dly <= hsin;
	hsout <= hsout_dly;
	
	vsout_dly <= vsin;
	vsout <= vsout_dly;
	
	blankout_dly <= blankin;	
	blankout <= blankout_dly;
	
	blank_ntsc_dly <= blank_NTSC;
	blank_ntsc_dly1 <= blank_ntsc_dly;
	end
reg	[3:0]	STATE,next;

always @ (posedge clk or negedge rst)
if(!rst)
	STATE <= 4'b1;
else
	STATE <= next;
	
always @ (STATE or blank_ntsc_dly1 or blank_ntsc_dly) begin
next = 4'b0;
case(1'b1)
	STATE[0]: if(blank_ntsc_dly)
			next[1] = 1'b1;
		  else
		  	next[0] = 1'b1;
	STATE[1]: if(!blank_ntsc_dly1)
			next[0] = 1'b1;
		  else
		  	next[2] = 1'b1;
	STATE[2]: next[1] = 1'b1;
	STATE[3]:;
endcase
end
wire	[7:0]	R_color,G_color,B_color;
reg	[7:0]	y0,cb,cr,y1;
always @ (posedge clk) begin
	y0 <= send_ram_rdb_raw[7:0];
	cr <= send_ram_rdb_raw[15:8];
	cb <= send_ram_rdb_raw[31:24];
	y1 <= send_ram_rdb_raw[23:16];
end

wire	[9:0]	y0_out,y1_out,cr_1p596,cb_2p017;
wire	[8:0]	cr_0p813,cb_0p392;
rom1p164_Y u0(
	.in(y0),
	.out(y0_out)
);	
rom1p596_Cr u1(
	.in(cr),
	.out(cr_1p596)
);	
rom0p813_Cr u2(
	.in(cr),
	.out(cr_0p813)
);
rom0p392_Cb u3(
	.in(cb),
	.out(cb_0p392)
);
rom2p017_Cb u4(
	.in(cb),
	.out(cb_2p017)
);
rom1p164_Y u5(
	.in(y1),
	.out(y1_out)
);

wire	[11:0]	sum1 =  y0_out + cr_1p596;
wire	[9:0]	r_reg0 = (sum1 > 9'd446)?(sum1-9'd446):1'b0;

wire	[11:0]	sum2 = y0_out + 9'd271;
wire	[11:0]	sum3 = cr_0p813 + cb_0p392;
wire	[9:0]	g_reg0 = (sum2 > sum3)?(sum2 - sum3):1'b0;

wire	[11:0]	sum4 = y0_out + cb_2p017;
wire	[9:0]	b_reg0 = (sum4 > 10'd554)?(sum4 - 10'd554):1'b0;	

wire	[11:0]	sum5 =  y1_out + cr_1p596;
wire	[9:0]	r_reg1 = (sum5 > 9'd446)?(sum5-9'd446):1'b0;

wire	[11:0]	sum6 = y1_out + 9'd271;
wire	[11:0]	sum7 = cr_0p813 + cb_0p392;
wire	[9:0]	g_reg1 = (sum6 > sum7)?(sum6 - sum7):1'b0;

wire	[11:0]	sum8 = y1_out + cb_2p017;
wire	[9:0]	b_reg1 = (sum8 > 10'd554)?(sum8 - 10'd554):1'b0;	

always @ (posedge clk or negedge rst)
if(!rst) begin
	pixel_R <= 1'b0;
	pixel_G <= 1'b0;
	pixel_B <= 1'b0;
	end
else if(STATE[1]) begin
	pixel_R <= blank_ntsc_dly ? (r_reg1[9]?8'd255:r_reg1[8:1]):8'h0;
	pixel_G <= blank_ntsc_dly ? (g_reg1[9]?8'd255:g_reg1[8:1]):8'h0;
	pixel_B <= blank_ntsc_dly ? (b_reg1[9]?8'd255:b_reg1[8:1]):8'h0;
	end
else if(STATE[2]) begin
	pixel_R <= blank_ntsc_dly ? (r_reg0[9]?8'd255:r_reg0[8:1]):8'h0;
	pixel_G <= blank_ntsc_dly ? (g_reg0[9]?8'd255:g_reg0[8:1]):8'h0;
	pixel_B <= blank_ntsc_dly ? (b_reg0[9]?8'd255:b_reg0[8:1]):8'h0;
	end
else begin
	pixel_R <= 1'b0;
	pixel_G <= 1'b0;
	pixel_B <= 1'b0;
	end

	
reg	[7:0]	send_ram_rab_reg1;
reg	send_ram_rab_hbit1;
always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_reg1 <= 1'b0;
else if(blank_ntsc_dly1) begin	
	if(STATE[1]) begin	
		if(send_ram_rab_reg1 == 8'd179)
			send_ram_rab_reg1 <= 1'b0;
		else
			send_ram_rab_reg1 <= send_ram_rab_reg1 + 1'b1;
		end
	end
else
	send_ram_rab_reg1 <= 1'b0;

always @ (posedge clk or negedge rst)
if(!rst)
	send_ram_rab_hbit1 <= 1'b0;
else if(send_ram_rab_reg1 == 'd179 && STATE[1])
	send_ram_rab_hbit1 <= ~send_ram_rab_hbit1;
else if(vsout)
	send_ram_rab_hbit1 <= 1'b0;

wire	[8:0]	send_ram_rab_raw = {send_ram_rab_hbit1,send_ram_rab_reg1};

always @ (posedge clk or negedge rst)
if(!rst)
	s_req_raw <= 1'b0;
else if(send_ram_rab_reg1==10'd30 || (!vsout_dly & vsout))
	s_req_raw <= 1'b1;
else if(s_ack_raw)
	s_req_raw <= 1'b0;
	
endmodule