add_mask.v

filter,很不错,大家可以看以下

module add_mask(
	rst,
	clk,					
	qd,
	
	qfv_odd,
	qfv_even,
	
	qd_out,
	qfv_out		//odd_frame first	
	);					
/*** ports ***/
input	rst;
input	[7:0]	qd;
input	clk;
input	qfv_odd,qfv_even;

output	[7:0]	qd_out;
output	qfv_out;

//internal 
parameter	MASK_ROW_TOP = 10'd1,MASK_ROW_BOTTOM = 10'd40;
reg	[7:0]	qd_dly,qd_dly1,qd_dly2,qd_dly3,qd_dly4,qd_dly5;
reg	qfv_dly,qfv_dly1,qfv_dly2,qfv_dly3,qfv_dly4,qfv_dly5,qfv_out;
always @ (posedge clk) begin
	qd_dly  <= qd;
	qd_dly1 <= qd_dly;
	qd_dly2 <= qd_dly1;
	qd_dly3 <= qd_dly2;
	qd_dly4 <= qd_dly3;
	qd_dly5 <= qd_dly4;
	
	qfv_dly <= qfv_odd | qfv_even;
	qfv_dly1 <= qfv_dly;
	qfv_dly2 <= qfv_dly1;
	qfv_dly3 <= qfv_dly2;
	qfv_dly4 <= qfv_dly3;
	qfv_dly5 <= qfv_dly4;
	qfv_out <= qfv_dly5;
	end

	
reg	[2:0]	STATE;
always @ (posedge clk or negedge rst)
if(!rst) begin
	STATE <= 1'b0;
	end
else 
	case(STATE)
	3'd0:	if(qfv_even)
			STATE <= 3'd1;
		else
			STATE <= 3'd0;
	3'd1:	if(qfv_odd)
			STATE <= 3'd2;
		else
			STATE <= 3'd1;
	3'd2:	if(qfv_dly)
			STATE <= 3'd3;
		else
			STATE <= 3'd2;
	3'd3:	if(!qfv_dly)
			STATE <= 3'd4;
		else
			STATE <= 3'd3;
	3'd4:	STATE <= 3'd2;
	endcase	
	

reg	[9:0]	row_cnt;
always @ (posedge clk or negedge rst)
if(!rst)
	row_cnt <= 1'b0;
else if(STATE == 3'd4)
	row_cnt <= row_cnt + 1'b1;
else if(row_cnt == 10'd288)
	row_cnt <= 1'b0;

reg	[1:0]	byte_cnt;
always @ (posedge clk or negedge rst)
if(!rst)
	byte_cnt <= 1'b0;
else if(qfv_dly)
	byte_cnt <= byte_cnt + 1'b1;
else
	byte_cnt <= 1'b0;

reg	[31:0]	data4byte_pre;
always @ (posedge clk or negedge rst)
if(!rst)
	data4byte_pre <= 31'd0;
else if(byte_cnt==2'd0)
	data4byte_pre[7:0] <= qd_dly;
else if(byte_cnt==2'd1)
	data4byte_pre[15:8] <= qd_dly;
else if(byte_cnt==2'd2)
	data4byte_pre[23:16] <= qd_dly;
else
	data4byte_pre[31:24] <= qd_dly;

reg	add_mask_ena;
always @ (posedge clk or negedge rst)
if(!rst)
	add_mask_ena <= 1'b0;
else if(row_cnt > 1'b1 && row_cnt<9'd40)
	add_mask_ena <= 1'b1;
else
	add_mask_ena <= 1'b0;
	
reg	[13:0]	r_ram_rab;
always @ (posedge clk or negedge rst)
if(!rst)
	r_ram_rab <= 1'b0;
else if(add_mask_ena & qfv_dly1 & (byte_cnt == 2'd3))
	r_ram_rab <= r_ram_rab + 1'b1;
else if(!add_mask_ena)
	r_ram_rab <= 1'b0;
				

wire	r_ram_rdb;
mask_rom mask_rom0(
	.clock(clk),
	.address(r_ram_rab),
	.q(r_ram_rdb)
	);
	
reg	[31:0]	data4byte;
always @ (posedge clk or negedge rst)
if(!rst)
	data4byte <= 31'd0;
else if((byte_cnt==2'd0) & qfv_dly1) begin
	if(add_mask_ena & r_ram_rdb) begin
		data4byte[31:24]<=8'd90;
		data4byte[23:16]<=8'd82;
		data4byte[15:8]<=8'd240;
		data4byte[7:0]<=8'd82;
		end
	else
		data4byte <= data4byte_pre;
	end


reg	[1:0]	byte_cnt_out;
always @ (posedge clk or negedge rst)
if(!rst)
	byte_cnt_out <= 1'b0;
else if(qfv_dly5)
	byte_cnt_out <= byte_cnt_out + 1'b1;
else 
	byte_cnt_out <= 1'b0;

reg	[7:0]	qd_out;
always @ (posedge clk or negedge rst)
if(!rst)
	qd_out <= 1'b0;
else if(qfv_dly5) begin
	if(byte_cnt_out == 2'd0)
		qd_out <= data4byte[7:0];
	else if(byte_cnt_out == 2'd1)
		qd_out <= data4byte[15:8];
	else if(byte_cnt_out == 2'd2)
		qd_out <= data4byte[23:16];
	else
		qd_out <= data4byte[31:24];
	end
else
	qd_out <= qd_dly5;
	
endmodule