clk_gen.v

来自「filter,很不错,大家可以看以下」· Verilog 代码 · 共 30 行

module clk_gen(
	clkin,
	rst,
	
	clkout
	);

input	clkin;
input	rst;

output	clkout;

reg	clkout;

reg	[1:0]	count;

always @ (posedge clkin or negedge rst)
if(!rst) begin
	count <= 0;
	clkout <= 0;
	end
else if(count == 'd3) begin
	clkout <= ~clkout;
	count <= 0;
	end
else
	count <= count + 1;

endmodule