receiver_data.v

filter,很不错,大家可以看以下

module receive_data(
	clk50m,
	rst,
	
	dck,
	data,
	req,
	
	r_ram_wab,
	r_ram_wdb,
	r_ram_wen,
	r_req,
	r_ack
	);

input	clk50m;
input	rst;
input	dck;
input	data;
input	req;

output	[12:0]	r_ram_wab;
output	r_ram_wdb;
outpu	r_ram_wen;
output	r_req;
input	r_ack;

reg	req_reg1,req_reg;
reg	data_reg1,data_reg;

always @ (posedge clk50m) begin
req_reg1 <= req;
req_reg <= req_reg1;
data_reg1 <= data;
data_reg <= data_reg1;
end

reg	[11:0]	r_ram_wab_reg;
always @ (posedge clk50m or negedge rst)
if(!rst)
	r_ram_wab_reg <= 0;
else if(req_reg) begin
	if(r_ram_wab_reg == 'd2879)
		r_ram_wab_reg <= 0;
	else
		r_ram_wab_reg <= r_ram_wab_reg + 1;
	end

reg	r_ram_wab_hbit;
always @ (posedge clk50m or negedge rst)
if(!rst)
	r_ram_wab_hbit <= 0;
else if(req_reg) begin
	if(r_ram_wab_reg == 'd2879)
		r_ram_wab_hbit <= ~r_ram_wab_hbit;
	end

wire	[12:0]	r_ram_wab = {r_ram_wab_hbit,r_ram_wab_reg};
always @ (posedge clk50m) begin
r_ram_wdb <= data_reg;
r_ram_wen <= req_reg;
end

reg	r_req;
always @ (posedge clk50m or negedge rst)
if(!rst)
	r_req <= 0;
else if(r_ram_wab_reg == 'd2879)
	r_req <= 1;
else if(r_ack)
	r_req <= 0;
	
endmodule