state.vhd

FPGA实验：用于检测输入的二进制系列

library ieee;
use ieee.std_logic_1164.all;
entity state is
	port(w:in std_logic_vector(16 downto 0);
		clk0,rst:in std_logic;	---取序列各位的时钟1Hz
		clk1:in std_logic;		---状态转换的时钟1KHz
		z:out std_logic);
end state;
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architecture state_switch of state is
	constant state0:std_logic_vector(7 downto 0):="00000000";
	constant state1:std_logic_vector(7 downto 0):="00000001";
	constant state2:std_logic_vector(7 downto 0):="00000010";
	constant state3:std_logic_vector(7 downto 0):="00000100";
	constant state4:std_logic_vector(7 downto 0):="00001000";
	constant state5:std_logic_vector(7 downto 0):="00010000";
	constant state6:std_logic_vector(7 downto 0):="00100000";
	constant state7:std_logic_vector(7 downto 0):="01000000";
	constant state8:std_logic_vector(7 downto 0):="10000000";
	signal current_state:std_logic_vector(7 downto 0);
	signal next_state:std_logic_vector(7 downto 0);
begin 
	process(rst,clk1)
	begin
		if rst='1' then current_state<=state0;
			elsif (clk1'event and clk1='1')then 
				current_state<=next_state;
		end if;
	end process;
	
	process(rst,clk0,current_state)
	variable cnt:integer range 0 to 17;	
	variable i:std_logic;
	begin
		if rst='1' or cnt=17 then cnt:=0;
			elsif clk0'event and clk0='1' then
			i:=w(cnt);
				case current_state is
			when state0=>z<='0';					
				if (i='0')then 
					next_state<=state5;
				elsif (i='1')then next_state<=state1;
				else next_state<=state0;
				end if;
			when state1=>z<='0';			
				if (i='0')then 
					next_state<=state5;
				elsif (i='1')then next_state<=state2;
				else next_state<=state1;
				end if;
			when state2=>z<='0';			
				if (i='0')then 
					next_state<=state5;
				elsif (i='1')then next_state<=state3;
				else next_state<=state2;
				end if;
			when state3=>z<='0';
				if (i='0')then 
					next_state<=state5;
				elsif (i='1')then next_state<=state4;
				else next_state<=state3;
				end if;
			when state4=>z<='1';
				if (i='0')then 
					next_state<=state5;
				elsif (i='1')then next_state<=state4;
				else next_state<=state4;
				end if;
			when state5=>z<='0';
				if (i='0')then 
					next_state<=state6;
				elsif (i='1')then next_state<=state1;
				else next_state<=state5;
				end if;
			when state6=>z<='0';
				if (i='0')then 
					next_state<=state7;
				elsif (i='1')then next_state<=state1;
				else next_state<=state6;
				end if;
			when state7=>z<='0';
				if (i='0')then 
					next_state<=state8;
				elsif (i='1')then next_state<=state1;
				else next_state<=state7;
				end if;
			when state8=>z<='1';
				if (i='0')then 
					next_state<=state8;
				elsif (i='1')then next_state<=state1;
				else next_state<=state8;
				end if;
			when others=>next_state<=state0;
		end case;
		cnt:=cnt+1;
		end if;	
	end process;
	----------------------------------
end state_switch;