state.hier_info

FPGA实验：用于检测输入的二进制系列

|state
w[0] => Mux0.IN31
w[1] => Mux0.IN30
w[2] => Mux0.IN29
w[3] => Mux0.IN28
w[4] => Mux0.IN27
w[5] => Mux0.IN26
w[6] => Mux0.IN25
w[7] => Mux0.IN24
w[8] => Mux0.IN23
w[9] => Mux0.IN22
w[10] => Mux0.IN21
w[11] => Mux0.IN20
w[12] => Mux0.IN19
w[13] => Mux0.IN18
w[14] => Mux0.IN17
w[15] => Mux0.IN16
w[16] => Mux0.IN15
clk0 => next_state[0].CLK
clk0 => next_state[1].CLK
clk0 => next_state[2].CLK
clk0 => next_state[3].CLK
clk0 => next_state[4].CLK
clk0 => next_state[5].CLK
clk0 => next_state[6].CLK
clk0 => next_state[7].CLK
clk0 => z~reg0.CLK
clk0 => cnt[0].CLK
clk0 => cnt[1].CLK
clk0 => cnt[2].CLK
clk0 => cnt[3].CLK
clk0 => cnt[4].CLK
rst => process1~0.IN1
rst => current_state[0].ACLR
rst => current_state[1].ACLR
rst => current_state[2].ACLR
rst => current_state[3].ACLR
rst => current_state[4].ACLR
rst => current_state[5].ACLR
rst => current_state[6].ACLR
rst => current_state[7].ACLR
clk1 => current_state[0].CLK
clk1 => current_state[1].CLK
clk1 => current_state[2].CLK
clk1 => current_state[3].CLK
clk1 => current_state[4].CLK
clk1 => current_state[5].CLK
clk1 => current_state[6].CLK
clk1 => current_state[7].CLK
z <= z~reg0.DB_MAX_OUTPUT_PORT_TYPE