state.tan.summary

来自「FPGA实验：用于检测输入的二进制系列」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.795 ns
From           : w[8]
To             : next_state[2]
From Clock     : --
To Clock       : clk0
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.444 ns
From           : z~reg0
To             : z
From Clock     : clk0
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.111 ns
From           : rst
To             : next_state[7]
From Clock     : --
To Clock       : clk0
Failed Paths   : 0

Type           : Clock Setup: 'clk0'
Slack          : N/A
Required Time  : None
Actual Time    : 268.67 MHz ( period = 3.722 ns )
From           : cnt[1]
To             : next_state[2]
From Clock     : clk0
To Clock       : clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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