state.map.rpt

FPGA实验：用于检测输入的二进制系列

; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                     ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                        ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------+
; state.vhd                        ; yes             ; User VHDL File  ; E:/lessons/电路与系统/实验设计/实验/state/state.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------+


+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary              ;
+---------------------------------------------+------------+
; Resource                                    ; Usage      ;
+---------------------------------------------+------------+
; Estimated Total logic elements              ; 42         ;
; Total combinational functions               ; 42         ;
; Logic element usage by number of LUT inputs ;            ;
;     -- 4 input functions                    ; 27         ;
;     -- 3 input functions                    ; 10         ;
;     -- <=2 input functions                  ; 5          ;
;         -- Combinational cells for routing  ; 0          ;
; Logic elements by mode                      ;            ;
;     -- normal mode                          ; 39         ;
;     -- arithmetic mode                      ; 3          ;
; Total registers                             ; 22         ;
; I/O pins                                    ; 21         ;
; Maximum fan-out node                        ; process1~0 ;
; Maximum fan-out                             ; 14         ;
; Total fan-out                               ; 213        ;
; Average fan-out                             ; 2.51       ;
+---------------------------------------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |state                     ; 42 (42)           ; 22 (22)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 21   ; 0            ; |state              ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 22    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 13    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 9     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |state|Mux5                ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |state|next_state~1        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------------------------+
; Source assignments for Top-level Entity: |state ;
+----------------+-------+------+-----------------+
; Assignment     ; Value ; From ; To              ;
+----------------+-------+------+-----------------+
; POWER_UP_LEVEL ; Low   ; -    ; cnt[0]          ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[1]          ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[2]          ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[3]          ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt[4]          ;
+----------------+-------+------+-----------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sun Oct 26 15:35:01 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off state -c state
Info: Found 2 design units, including 1 entities, in source file state.vhd
    Info: Found design unit 1: state-state_switch
    Info: Found entity 1: state
Info: Elaborating entity "state" for the top level hierarchy
Info: Implemented 71 device resources after synthesis - the final resource count might be different
    Info: Implemented 20 input pins
    Info: Implemented 1 output pins
    Info: Implemented 50 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Oct 26 15:35:07 2008
    Info: Elapsed time: 00:00:07